产学研教授 深港微电子学院
陈凯教授博士毕业于美国加州大学伯克利分校电子工程与计算机科学系,曾任职于美国国家半导体公司(现德克萨斯仪器)费尔柴尔德研究中心和IBM半导体研发中心,并有近20年在中美两国的创业经历。2021年加入南方科技大学,任深港微电子学院产学研教授和未来通信集成电路教育部工程研究中心执行主任。
个人简介
研究领域
前沿CMOS器件物理、器件结构与设计、器件建模和工艺集成,特别是用于量子计算的(4.2K-10mK)低温cryogenic CMOS器件物理和电路设计用建模。
教学
1.微电子前沿创新与技术领导力;
2.硅基量子计算低温CMOS。
学术成果 查看更多
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Hao Su, Yunfeng Xie, Yuhuan Lin, Haihan Wu, Wenxin Li, Zhizhao Ma, Yiyuan Cai, Xu Si, Shenghua Zhou, Guangchong Hu, Yu He, Feichi Zhou, Xiaoguang Liu, Longyang Lin, Yida Li, Hongyu Yu and Kai Chen (2024), “Characterizations and Framework Modeling of Bulk MOSFET Threshold Voltage Based on a Physical Charge-Based Model Down to 4 K,” presented at the 50th ESSERC, Bruges, Belgium.
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Hao Su, Yiyuan Cai, Shenghua Zhou, Guangchong Hu, Yu He, Yunfeng Xie, Yuhuan Lin, Chunhui Li, Tianqi Zhao, Jun Lan, Wenhui Wang, Wenxin Li, Feichi Zhou, Xiaoguang Liu, Longyang Lin, Yida Li, Hongyu Yu and Kai Chen (2024), “A Physical Charge-Based Analytical Threshold Voltage Model for Cryogenic CMOS Design,”IEEE Journal of the Electron Devices Society, pp. 1–1, 2024, doi:10.1109/JEDS.2024.3359664.
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Hao Su, Yiyuan Cai, Shenghua Zhou, Guangchong Hu, Yu He, Yunfeng Xie, Yuhuan Lin, Chunhui Li, Tianqi Zhao, Jun Lan, Wenhui Wang, Wenxin Li, Feichi Zhou, Xiaoguang Liu, Longyang Lin, Yida Li, Hongyu Yu and Kai Chen (2024), “Investigation of Long Channel Bulk MOSFETs Threshold Voltage Model Down to 10 mK and Key Analog Parameters at 4 K,”. International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, 37(3), e3258. https://doi.org/10.1002/jnm.3258
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Kai Chen and Chenming Hu, “Performance and Vdd Scaling in Deep Submicrometer CMOS”, IEEE Journal of Solid-State Circuit(JSSC), vol. 33, no. 10, pp. 1586-1589, October 1998;
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Kai Chen, Chenming Hu, and Peng Fang, “Optimizing Quarter and Sub-Quarter Micron CMOS Circuit Speed Considering Interconnect Loading Effect”, IEEE Transactions on Electron Devices (T-ED), Vol. 44, No. 9, 1997;
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Zhenbiao Li, Wenhai Ni, Jie Ma, Ming Li, Dequn Ma, Dong Zhao, Mehta J., D. Harman, Xianfeng Wang, K.K. O and Kai Chen, “A dual-Band CMOS Transceiver for 3G TD-SCDMA”, Digest of Technical Papers, IEEE International Solid-State Circuits Conference (ISSCC), pages 344-607, Feb. 2007;
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Isabel Yang, Kai Chen and Lisa Su et al, “Sub-60nm Physical Gate Length SOI CMOS”, IEEE Electronics Device Meeting (IEDM) 1999.