产学研教授 深港微电子学院   课题组网站

陈凯教授博士毕业于美国加州大学伯克利分校电子工程与计算机科学系,曾任职于美国国家半导体公司(现德克萨斯仪器)费尔柴尔德研究中心和IBM半导体研发中心,并有近20年在中美两国的创业经历。2021年加入南方科技大学,任深港微电子学院产学研教授和未来通信集成电路教育部工程研究中心执行主任。

个人简介

研究领域

1.前沿器件物理、器件结构与设计、器件建模和工艺集成,包括量子计算2K-10mK超低温CMOS器件的物理、建模和RF/模拟电路,硅光集成,神经形态类脑人工智能(neuromorphic AI)元器件,以及三维(3D)器件的结构与设计等;

2.电子元器件与可穿戴设备在健康领域的应用,特别是院外环境下,按“精准医学”进行每个生命个体全生命周期全方位的健康数据采集、分析、云计算和介入管理;

3.微纳电子领域的科技创业与社会,包括区域/国家科技政策与战略。


教学

1.微电子科技、产业、政策与博弈;

2.量子计算硅工艺器件入门。


学术成果 查看更多

  1. Kai Chen and Chenming Hu, “Performance and Vdd Scaling in Deep Submicrometer CMOS”, IEEE Journal of Solid-State Circuit(JSSC), vol. 33, no. 10, pp. 1586-1589, October 1998;
  2. Kai Chen, Chenming Hu, Peng Fang, Min Ren Lin and Donald L. Wollesen “Predicting CMOS Speed with Gate Oxide and Voltage Scaling and Interconnect Loading Effects”, IEEE Transactions on Electron Devices (T-ED), Vol. 44, No. 11, 1997;Isabel Yang, Kai Chen and Lisa Su et al, “Sub-60nm Physical Gate Length SOI CMOS”, IEEE Electronics Device Meeting (IEDM) 1999;
  3. Kai Chen, Chenming Hu, and Peng Fang, “Optimizing Quarter and Sub-Quarter Micron CMOS Circuit Speed Considering Interconnect Loading Effect”, IEEE Transactions on Electron Devices (T-ED), Vol. 44, No. 9, 1997;
  4. Kai Chen, Chenming Hu, Peng Fang, and Ashawant Gupta, “Experimental Confirmation of An Accurate CMOS Gate Delay Model for Gate Oxide and Voltage Scaling”, IEEE Electron Device Letters (EDL), Vol. 18, No. 6, pp. 275-277, June 1997;
  5. Kai Chen, H. C. Wann, J. Duster, M. Yoshida, P. Ko and C. Hu, “MOSFET Carrier Mobility Model Based on Gate Oxide Thickness, Threshold and Gate Voltages”, IEEE Journal of Solid-State Electronics (SSE), pp. 1515-1518, Vol. 39, No. 10, October 1996;
  6. Kai Chen, C. H. Wann, J. Duster, P. Ko and C. Hu, “The Impact of Device Scaling and Supply Voltage Change on CMOS Gate Performance”, IEEE Electron Device Letters (EDL), pp. 202-204, Vol. 17, No. 5, May 1996.
  7. Kai Chen, H. C. Wann, J. Duster, P. Pramanik, S. Nariani, P. Ko and C. Hu, “An Accurate Semi-Empirical Saturation Drain Current Model for LDD NMOSFET”, IEEE Electron Device Letters (EDL), pp. 145-147, Vol. 17, No. 3, March 1996;
  8. Kai Chen, Jian-hui Huang, James Z. Ma, Z.H. Liu, M.C. Jeng, Ping K. Ko and Chenming Hu, “Polysilicon Gate Depletion Effect on IC Performance”, IEEE Journal of Solid-State Electronics, pp. 1975-1977, Vol. 38, No. 11, November 1995;
  9. Qiuxia Xu and Kai Chen, “Physical Thickness 1.5nm HfZrO Negative Capacitance NMOSFETs”, submitted to IEEE Transactions on Electronics Devices (TED) accepted on 21, 2021;
  10. Zhenbiao Li, Wenhai Ni, Jie Ma, Ming Li, Dequn Ma, Dong Zhao, Mehta J., D. Harman, Xianfeng Wang, K.K. O and Kai Chen, “A dual-Band CMOS Transceiver for 3G TD-SCDMA”, Digest of Technical Papers, IEEE International Solid-State Circuits Conference (ISSCC), pages 344-607, Feb. 2007;
  11. Isabel Yang, Kai Chen and Lisa Su et al, “Sub-60nm Physical Gate Length SOI CMOS”, IEEE Electronics Device Meeting (IEDM) 1999.

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联系地址

广东省深圳市南山区智园崇文园区3号楼434

办公电话

电子邮箱

Chenk6@sustech.edu.cn

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