Professor of Industry and Research School of System Design and Intelligent Manufacturing   Research Group

Dr. Kai Chen graduated from the Department of Electrical Engineering and Computer Science at the University of California, Berkeley, and worked at the Fairchild Research Center of National Semiconductor Corporation (now Texas Instruments) and IBM Semiconductor R&D Center, and has nearly 20 years of entrepreneurial experience in China and the U.S. He joined Southern University of Science and Technology in 2021 as Professor of Industry-Academia-Research in the Shenzhen-Hong Kong Institute of Microelectronics and Executive Director of the Future Communication Integrated Circuit Executive Director of Engineering Research Center, Ministry of Education.

Personal Profile


1. cutting-edge device physics, device structure and design, device modeling and process integration, including quantum computing 2K-10mK ultra-low temperature CMOS device physics, modeling and RF/analog circuits, silicon optical integration, neuromorphic AI components, and three-dimensional (3D) device structure and design, etc..

2. Electronic components and wearable devices in the field of health applications, especially in the out-of-hospital environment, according to the "precision medicine" for each individual life cycle of all-round health data collection, analysis, cloud computing and intervention management.

3. Science and technology entrepreneurship and society in the field of micro and nano electronics, including regional/national science and technology policies and strategies.


1. microelectronics technology, industry, policy and gaming.

2. Introduction to silicon process devices for quantum computing.

Publications Read More

  1. Kai Chen and Chenming Hu, “Performance and Vdd Scaling in Deep Submicrometer CMOS”, IEEE Journal of Solid-State Circuit(JSSC), vol. 33, no. 10, pp. 1586-1589, October 1998;
  2. Kai Chen, Chenming Hu, Peng Fang, Min Ren Lin and Donald L. Wollesen “Predicting CMOS Speed with Gate Oxide and Voltage Scaling and Interconnect Loading Effects”, IEEE Transactions on Electron Devices (T-ED), Vol. 44, No. 11, 1997;Isabel Yang, Kai Chen and Lisa Su et al, “Sub-60nm Physical Gate Length SOI CMOS”, IEEE Electronics Device Meeting (IEDM) 1999;
  3. Kai Chen, Chenming Hu, and Peng Fang, “Optimizing Quarter and Sub-Quarter Micron CMOS Circuit Speed Considering Interconnect Loading Effect”, IEEE Transactions on Electron Devices (T-ED), Vol. 44, No. 9, 1997;
  4. Kai Chen, Chenming Hu, Peng Fang, and Ashawant Gupta, “Experimental Confirmation of An Accurate CMOS Gate Delay Model for Gate Oxide and Voltage Scaling”, IEEE Electron Device Letters (EDL), Vol. 18, No. 6, pp. 275-277, June 1997;
  5. Kai Chen, H. C. Wann, J. Duster, M. Yoshida, P. Ko and C. Hu, “MOSFET Carrier Mobility Model Based on Gate Oxide Thickness, Threshold and Gate Voltages”, IEEE Journal of Solid-State Electronics (SSE), pp. 1515-1518, Vol. 39, No. 10, October 1996;
  6. Kai Chen, C. H. Wann, J. Duster, P. Ko and C. Hu, “The Impact of Device Scaling and Supply Voltage Change on CMOS Gate Performance”, IEEE Electron Device Letters (EDL), pp. 202-204, Vol. 17, No. 5, May 1996.
  7. Kai Chen, H. C. Wann, J. Duster, P. Pramanik, S. Nariani, P. Ko and C. Hu, “An Accurate Semi-Empirical Saturation Drain Current Model for LDD NMOSFET”, IEEE Electron Device Letters (EDL), pp. 145-147, Vol. 17, No. 3, March 1996;
  8. Kai Chen, Jian-hui Huang, James Z. Ma, Z.H. Liu, M.C. Jeng, Ping K. Ko and Chenming Hu, “Polysilicon Gate Depletion Effect on IC Performance”, IEEE Journal of Solid-State Electronics, pp. 1975-1977, Vol. 38, No. 11, November 1995;
  9. Qiuxia Xu and Kai Chen, “Physical Thickness 1.5nm HfZrO Negative Capacitance NMOSFETs”, submitted to IEEE Transactions on Electronics Devices (TED) accepted on 21, 2021;
  10. Zhenbiao Li, Wenhai Ni, Jie Ma, Ming Li, Dequn Ma, Dong Zhao, Mehta J., D. Harman, Xianfeng Wang, K.K. O and Kai Chen, “A dual-Band CMOS Transceiver for 3G TD-SCDMA”, Digest of Technical Papers, IEEE International Solid-State Circuits Conference (ISSCC), pages 344-607, Feb. 2007;
  11. Isabel Yang, Kai Chen and Lisa Su et al, “Sub-60nm Physical Gate Length SOI CMOS”, IEEE Electronics Device Meeting (IEDM) 1999.

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