助理教授 深港微电子学院

潘权博士,中国科学技术大学电子科学与技术专业学士,香港科技大学电子及计算机工程学专业博士。2005年到2009年在北京时代民芯科技有限公司担任射频芯片工程师。2014年到2018年在美国硅谷高速硬件创业公司eTopus Technology Inc. 担任高级主管工程师。主要研究工作集中在高速模拟/射频集成电路设计,主要包括:Wireline/Wireless高速通信集成电路、光通信集成电路、Serdes/clock and data recovery(CDR)电路、低噪声放大器/频率综合器、硅光互连研究。作为课题负责人不仅在国际主流会议/期刊上发表40多篇高水平学术论文,同时有超过8年丰富的国内外工作经验,包括4年硅谷业界最前沿的工作经验。于2014年获得第四届香港科大百万创业大赛创新奖,2017 年获得IEEE电路系统协会授予杰出青年作者奖, 2019年获得“珠江人才计划”引进高层次人才项目-青年拔尖人才。

个人简介

潘权博士,主要研究工作集中在高速模拟/射频集成电路设计,主要包括:Wireline/Wireless高速通信集成电路(接收机/发射机)、Serdes/clock and data recovery(CDR)电路、低噪声放大器/频率综合器、GaN集成电路、硅光互连研究。课题负责人不仅在国际主流会议/期刊上发表多篇高水平学术论文,同时有超过8年丰富的国内外工作经验,包括4年硅谷业界最前沿的工作经验。

科研工作经历

2018-至今 南方科技大学,助理教授

2014-2018 美国硅谷高速硬件创业公司eTopus Tech. Inc.,高级主管工程师

2005-2009北京时代民芯科技有限公司,射频电路工程师

教育背景

2014 香港科技大学电子及计算机工程学系,博士学位

2005 中国科学技术大学电子科学与技术系,学士学位

主要荣誉

2019 “珠江人才计划”引进高层次人才项目-青年拔尖人才

2017 杰出青年作者奖, IEEE电路系统协会

2014 创新奖,第四届香港科大百万创业大赛

研究领域

高速光通信集成电路

Serdes/CDR电路

模拟/射频集成电路

硅光互连研究

GaN集成电路设计

 

学术任职

现担任以下期刊的审稿人:

  1. IEEE Journal of Solid-State Circuits
  2. IEEE Transactions on Microwave Theory and Techniques
  3. IEEE Transactions on Circuits and Systems I/II
  4. IEEE Photonics Technology Letter
  5. IEEE Journal of Lightwave Technology
  6. IEEE Transactions on Very Large Scale Integration (VLSI) Systems

现担任以下项目的评审人:

  1. 国家自然科学基金面上项目通讯评审
  2. 广东省自然科学基金项目评审
  3. 深圳市科创委员会项目评审

 

指导研究生和本科生成果
 欢迎基础扎实,成绩好的同学加入我们团队,从事前沿芯片设计!
 强调理论分析能力、解决问题能力、个人综合能力的全面提升,成为具有国际视野的芯片设计师和未来的领导者!

指导学生奖项

§   2021年,本科毕业生丘璋,朱思强,徐东藩,范怡然,周文韬,蔡平易,南方科技大学优秀本科毕业论文

§   2021年,本科毕业生丘璋,朱思强,徐东藩,南方科技大学工学院综合设计二等奖

§   2021年,本科毕业生范怡然,蔡平易,樊昕,南方科技大学工学院综合设计三等奖

§   2020年,硕士研究生胡俊峰,南方科技大学第二届工程硕士毕业成果一等奖

§   2020年,本科毕业生朱俊桦,钟宇昕,南方科技大学优秀本科毕业论文

§   2020年,本科毕业生李正浩,唐敏哲,樊泰扬,陆煜晨,南方科技大学工学院综合设计一等奖

研究领域

光通信集成电路, Wireline/Serdes/TIA/CDR电路

模拟/射频集成电路,5G/毫米波集成电路设计 (CMOS, GaN等)

芯片级和板级EMI和噪声分析,高性能版图优化分析

硅光互连研究


教学

主讲课程:模拟集成电路设计(本科),射频通信集成电路与系统设计(研究生)

参讲课程:暂无

指导学生奖项:

§ 2021年,本科毕业生丘璋,朱思强,徐东藩,范怡然,周文韬,蔡平易,南方科技大学优秀本科毕业论文

§ 2021年,本科毕业生丘璋,朱思强,徐东藩,南方科技大学工学院综合设计二等奖

§ 2021年,本科毕业生范怡然,蔡平易,樊昕,南方科技大学工学院综合设计三等奖

§ 2020年,硕士研究生胡俊峰,南方科技大学第二届工程硕士毕业成果一等奖

§ 2020年,本科毕业生朱俊桦,钟宇昕,南方科技大学优秀本科毕业论文

§ 2020年,本科毕业生李正浩,唐敏哲,樊泰扬,陆煜晨,南方科技大学工学院综合设计一等奖

欢迎基础扎实,成绩好的同学加入我们团队,从事前沿芯片设计!

强调理论分析能力、解决问题能力、个人综合能力的全面提升,成为具有国际视野的芯片设计师和未来的领导者!


学术成果 查看更多

研究成果主要发表在IEEE等学术期刊及相关会议上,代表文章有:

[J17] Q. Pan*, X. Luo, “A 58-dBΩ 20-Gb/s inverter-based cascode transimpedance amplifier for optical communications,” in Journal of Semiconductors(JOS), 2021. (Accepted)

[J16] H. Mosalam, Q. Pan*, “A 57–100 ​GHz 0.13 ​μm SiGe power amplifier with high output power and efficiency,”Microeletronics Journal, 2021.

[J15] J. Zhu, Q. Jiang, H. Mosalam, C. Zhan, Q. Pan*, “A 19-48.3-GHz 6th-order Transformer Based Injection locked Frequency Divider with  87.1% Locking Range in 40-nm CMOS,” IEEE Transactions on Circuits and Systems II: Express Briefs, 2021.

[J14] H. Mosalam, W. Xiao, X. Gui, D.  Li, Q. Pan*, “A 54-68 GHz Power Amplifier with Improved Linearity and Efficiency in 40 nm CMOS,” IEEE Transactions on Circuits and System II: Express Briefs, 2021.

[J13] H. Mosalam, W. Xiao, Q. Pan*, “A 50-82 GHz Broadband Cascode-Based Power Amlifier in 40 nm CMOS,” International Journal of Electronics and Communications, 2021.

[J12] Z. Li, M. Tang, T. Fan, Q. Pan*, “A 56-Gb/s PAM4 Receiver Analog Front-End with Fixed Peaking Frequency and Bandwidth in 40-nm CMOS,” IEEE Transactions On Circuits And Systems II: Express Briefs, 2021.

[J11] Q. Huang, C. Zhan*, L. Wang, Z. Li, Q. Pan*, “A -40 ∘C to 120 ∘C, 169 ppm/∘C Nano-Ampere CMOS Current Reference,” IEEE Transactions On Circuits And Systems II: Express Briefs, issue. 67(9), pp. 1494-1498, 2020.

[J10] Q. Pan*,L. Wang, X. Luo, and C. P. Yue, “A Low-Power PAM4 Receiver with an Adaptive Variable-Gain Rectifier Based Decoder ,”IEEE Transactions on Very Large Scale Integration (VLSI) Systems,  issue. 28(10), pp. 2099-2108, 2020.

[J09] J. Hu, Z. Zhang , Q. Pan*, “A 15-Gb/s 0.0037-mm2 0.019-pJ/Bit Full-Rate Programmable Multi-Pattern Pseudo-Random Binary Sequence Generator,”IEEE Transactions On Circuits And Systems II: Express Briefs, issue. 67(9), pp. 1499-1503, 2020.

[J08] Q. Pan*, Y. Wang, and C. P. Yue, “A 42-dB Ω 25 -Gb/s CMOS Transimpedance Amplifier with Multiple-Peaking Scheme for Optical Communications,”IEEE Transactions On Circuits And Systems II: Express Briefs, issue. 67(1), pp. 72−76, 2020.

[J07] J. Wang, Q. Pan* et al., “A Fully-Integrated 25Gb/s Low-Noise TIA+CDR Optical Receiver Designed in 40nm-CMOS,” TCAS-II, DOI 10.1109/TCSII.2019.2925363, Jun. 2019.

[J06] Y. Wang, D. Luo, Q. Pan, L. Jing, Z. Li, and C. P. Yue, “A 60-GHz 4-Gb/s Fully Integrated NRZ-to-QPSK Fiber-Wireless Modulator,” IEEE Transactions of Circuits and Systems−I (TCAS-I), vol. 64, issue. 3, pp. 653−663, Mar. 2017.

[J05] Q. Pan*, Y. Wang, Y. Lu, and C. P. Yue, “An 18-Gb/s Fully Integrated Optical Receiver with Adaptive Cascaded Equalizer,” IEEE Journal of Selected Topics in Quantum Electronics (JSTQE), vol. 22, no. 6, Nov./Dec. 2016. (Top-level optical/electrical journal. CMOS optical receiver research including both

optical device and electrical circuits)

[J04] Y. Lu, Y. Wang, Q. Pan, C. P. Yue, and W. H. Ki, “A Fully-Integrated Low-Dropout Regulator with Ultra-Fast Transient Response and Full-Spectrum Power Supply Rejection,“IEEE Transactions of Circuits and Systems−I (TCAS-I), vol. 63, no. 3, pp. 707−716, Mar. 2015.

[J03] Q. Pan*, Y. Wang, Z. Hou, L. Sun, Y. Lu, L. Wu, W. H. Ki, P. Chiang, and C. P. Yue, “A 30-Gb/s 1.37-pJ/b CMOS Receiver for Optical Interconnects,“IEEE Journal of Lightwave Technology (JLT), vol. 33, no. 4, pp. 778−786, Feb. 2015. (Top-level optical journal. High-speed CMOS optical circuits research)

On/Before 2014:

[J02] L. Sun, Q. Pan, K. C. Wang, and C. P. Yue, “A 26-28-Gb/s clock and data recovery circuit with embedded equalizer in 65-nm CMOS,” IEEE Transactions of Circuits and Systems−I (TCAS-I), vol. 61, no. 7, pp. 2139−2149, Jul. 2014.

[J01] Q. Pan*, Z. Hou, Y. Li, A. W. Poon, and C. P. Yue, “A 0.5-V P-Well/Deep N-Well photodetector in 65-nm CMOS for monolithic 850-nm optical receivers,”IEEE Photonics Technology Letters (PTL), vol. 26, no. 12, pp. 1184−1187, Jun. 2014. (Top-level optical journal. Optical device research)

Conference Papers

[C26] Z. Qiu, X. Luo, Z. Li, S. Zhu, L. Wang, Z. Mao, X. Gui, D. Li, Q. Pan*, “A 720-m Vpp 224-Gb/s PAM4 Optical Receiver with Multiple Peaking Techniques in 130-nm SiGe BiCMOS,” IEEE Asia Pacific Conference on Circuits and Systems(APCCAS), 2021. (Accepted)

[C25] Q. Jiang and Q. Pan, ” Tuning-Less Injection-Locked Frequency Dividers with Wide Locking Range Utilizing 8th-Order Transformer-Based Resonator,” in IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2021.

[C24] D. Li, S. Gao, Y. Shi, X. Gui, N. Qi, Z. Li, Q. Pan, P. Chiang, L. Geng, “A 112-Gb/s PAM-4 Linear Optical Receiver in 130-nm SiGe BiCMOS,” 2020 IEEE International Symposium on Circuits and Systems (ISCAS).2020

[C23] D. Xu, Y. Kou, P. Lai, Z. Cheng, T. Y. Cheung, L. Moser, Y. Zhang, X. Liu, M. P. Lam, H. Jia, Q. Pan, W. H. Szeto, C. F. Tang, K. F. Mak, K. Sarfraz, T. Zhu, M. Kwan, E. Y. L. Au, C. Conroy, K. K. Chan, “A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed MMSE CDR in 16nm and 7nm,” 2020 International Solid-State Circuit Conference(ISSCC).2020

[C22] D. Xu, Z. Qiu, X. Luo, X. You, W. Xiao, S. Zhu, M. Tang, Z. Li, Q. Pan, “Fully-Differential 100-Gb/s PAM4 Cross-Coupled Regulated Transimpedance Amplifier”  2020 IEEE International Conference on Integrated Circuits, Technologies and ApplicationsICTA.2020

[C21] J. Fu, P. Cai, X. Luo, X. You, L. Zhong, W. Xiao, F. L., Yao Li , Q. Pan, “A 224-Gb/s PAM4 High-Linearity, Energy-Efficiency Differential to Single-Ended Driver in 130-nm SiGe BiCMOS,” 2020 IEEE International Conference on Integrated Circuits, Technologies and ApplicationsICTA.2020

[C20] Xin Wang, Yi Peng, Yuanxi Zhang, Tao Xia, Yifan Wu, Juncheng Wang, Lei Wang, Liujia Song, Lei Zhao, Shenglong Zhuo, Quan Pan, Xuefeng Chen, Patrick Yin Chiang and Rui Bai,”A 25Gb/s-PAM4 Optical Transceiver Chipset for 5G Optical Front-Haul ”2020 Optical Fiber Communications Conference and Exhibition (OFC).2020

[C19] J. Hu, Z. Zhang, Q. Huang, J. Yang, M. Hu, Q. Jiang Y. Guo, Q.Pan “An 18-Gb/s 36×13-µm2 3.53-mW 2^7-1 PRBS Generator in 40-nm CMOS,”2020 IEEE International Conference on Electronics, Information, and Communication (ICEIC), Barcelona, Spain, Jan. 2020

[C18] M. Tang, Z. Li, J. Hu, Q. Huang, N, Qi, H.Yu, Q. Pan, “A 56-Gb/s PAM4 Continuous-Time Linear Equalizer with Fixedin Peaking Frequency in 40-nm CMOS,” 2019 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA), Cheng’du, China, Nov. 2019.

[C17] S. Hu, T. Yao, T. Yao, B. Yin, C. Song, L. Zhao, J. Wang, R. Bai, X. Wang, T. Xia, Y. Peng, B. Yao, Y. Li, Q. Pan, Nan Qi, X. Chen, P. Y. Chiang, “A 50Gb/s PAM-4 Retimer-embedded VCSEL Driver with Asymmetric Pulsed Pre-emphasis in 40nm CMOS”, Optical Fiber Communication Conference and Exhibit. Technical Digest (OFC), Mar. 2019.

[C16] Z. Li, M. Tang, Y. Guo, Q. Huang and Q. Pan, “A 56-Gb/s PAM4 Variable Gain Amplifier in 40-nm CMOS Technology,” in 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Xi’an, China, 2019, pp. 1―3.

[C15] Y. Guo and Q. Pan, “A PAM-4 80-Gb/S Variable-Gain Transimpedance Amplifier in 40-nm CMOS Technology,”in IEEE International Conference on Integrated Circuits,Technologies and Applications, Nov. 2018.

[C14] G. Zhu, Q. Pan, J. Zhuang, C. Zhi, and C. P. Yue, “A Low-Power PAM4 Receiver Using 1/4-Rate Sampling Decoder with Adaptive Variable-Gain Rectification,” in 2017 IEEE Asian Solid-State Circuits Conf., Nov. 2017.

[C13] Y. Wang, D. Luo, Q. Pan, L. Jing, Z. Li, and C. P. Yue, “A 60GHz 4Gb/s Fully Integrated NRZ-to-QPSK Modulator SoC for Backhaul Links in Fiber-Wireless Networks,”in Proc. European Solid-State Circuits Conf., Sep. 2015.

On/Before 2014:

[C12] Q. Pan, Y. Wang, Z. Hou, L. Sun, L. Wu, W. H. Ki, P. Chiang, and C. P. Yue, “A 41-mW 30-Gb/s CMOS Optical Receiver with Digitally-Tunable Cascaded Equalization,”in Proc. European Solid-State Circuits Conf., Sep. 2014. (Top-level circuits conference. High-speed CMOS optical circuits)

[C11] Q. Pan, L. Sun, and C. P. Yue, “Differential Stacked Spiral Inductor and Transistor Layout Designs for Broadband High-Speed Circuits,”in IEEE Radio Frequency Integration Technology, Aug. 2014. (International device/circuits conference. RF inductor device research)

[C10] Y. Wang, Y. Lu, Q. Pan, Z. Hou, L. Wu, W. H. Ki, and C. P. Yue, “A 3-mW 25-Gb/s CMOS transimpedance amplifier with fully integrated low-dropout regulator for 100GbE systems,”in IEEE Radio Frequency Integrated Circuits Symp., pp. 275−278, Jun. 2014.

[C09] Q. Pan, Z. Hou, Y. Wang, Y. Lu, W. H. Ki, K. C. Wang, and C. P. Yue, “A 48-mW 18-Gb/s Fully Integrated CMOS Optical Receiver with Photodetector and Adaptive Equalizer,”in Symp. VLSI Circuits Dig. Tech. Papers, pp. 116−117, Jun. 2014. (Top-level circuits conference. High-speed CMOS optical system with both device and circuits research)

[C08] Y. Wang, Y. Lu, Q. Pan, Z. Hou, L. Wu, W. H. Ki, and C. P. Yue, “A 3-mW 25-Gb/s CMOS transimpedance amplifier with fully integrated low-dropout regulator for 100GbE systems,”in IEEE Radio Frequency Integrated Circuits Symp., pp. 275−278, Jun. 2014.

[C07] Z. Hou, Q. Pan, Y. Wang, L. Wu, and C. P. Yue, “A 23-mW 30-Gb/s digitally programmable limiting amplifier for 100GbE optical receivers,”in IEEE Radio Frequency Integrated Circuits Symp., pp. 279−282, Jun. 2014.

[C06] Q. Pan, Z. Hou, Y. Wang, and C. P. Yue, “A 65-nm CMOS P-well/Deep N-well avalanche photodetector for integrated 850-nm optical receivers,”in IEEE 10th International Conference on ASIC, Oct. 2013. (International device-level conference. Optical photodetector device research)

[C05] L. Sun, Q. Pan, K. C. Wang, and C. P. Yue, “A 25-28 Gbps clock and data recovery system with embedded equalization in 65-nm CMOS,”in Inter. Conference on Solid-State and Integrated Circuit Tech., Oct. 2012.

[C04] Q. Pan, T. J. Yeh, C. Jou, F. L. Hsueh, H. Luong, and C. P. Yue, “A performance study of layout and Vt options for low noise amplifier design in 65-nm CMOS,”in IEEE Radio Frequency Integrated Circuits Symp., pp. 535−538, Jun. 2012. (Top-level circuits conference. High-speed CMOS LNA circuits with device research for TSMC project – transistor study)

[C03] D. Zhang, Z. Wen, W. Li, Q. Pan, “A Large Gain Variable Range, Wide Band width Analog AGC Circuitry for a CMOS GPS Receiver”, Robot World 2008, Seoul, Korea, Oct. 2008.

[C02] Q. Pan, Z. Wen, and W. Li, “A 1.57-GHz low-power low-phase-noise quadrature LC-VCO,”in WCECS 2008, pp. 192‒195, Oct. 2008.

[C01] Q. Pan, Z. Wen, Y. Zhang, and B. Bi, “Phase Noise and Power Optimization of a 2-GHz Differential CMOS LC VCO,”in IEEE Radio Frequency Integration Technology,pp. 258‒261, Aug. 2007.

新闻动态 更多新闻

  • 课题组胡俊峰同学获得南方科技大学第二届工程硕士毕业成果展一等奖

    2020-07-09
  • 课题组朱俊桦同学获得优秀毕业论文荣誉

    2020-07-09
  • 课题组钟宇昕同学获得优秀毕业论文荣誉

    2020-07-07

团队成员 查看更多

加入团队

南方科技大学电子系 模拟/通信集成电路设计方向 诚聘博士后/博士生/硕士生/研究助理

 

课题组介绍:

本课题组的主要研究方向是:通信集成电路(接收机/发射机)、Serdes/clock and data recovery(CDR)电路、毫米波集成电路、硅光互连研究。拟招聘博士后/博士生/硕士生/研究助理

 

应聘要求

研究领域

1) Wireline/Optical通信集成电路设计(transceiver), TIA/CTLE/DFE/ FFE/LA/Driver, Serdes/clock and data recovery circuits;

2) Wireless射频集成电路设计,LNA/mixer/VGA/frequency synthesizer/PA,毫米波IC设计。

3)硅光互连研究

 

博士后岗位

1) 已取得或即将取得博士学历学位;

2) 热爱科学研究、勤奋努力、具有主动性、强烈的进取心;

3) 能够熟练使用英文进行交流,能够完成研究论文的撰写;

4) 在国内外刊物以第一作者身份发表过较高水平科研论文;

5) 具有模拟/射频/高速电路设计经验经历者优先考虑。

 

研究助理岗位

1) 取得或将取得相关专业的学士以上学位;

2) 具有良好的英文读,写,说能力和计算机操作能力;

3) 具有模拟/射频/高速电路设计经验经历者优先考虑。

 

岗位待遇

博士后待遇
1)参照《南科大博士后管理办法》及深圳市相关人才引进条例,年薪30万元(含市政补贴税后18万元/年);提供2800元/月住房补贴(如户口迁往深圳,还可额外获得政府免税住房补贴3万元),餐补220元/月。优秀者可申请校长卓越博士后,年薪35万/年。

2)享受正式教职工待遇((含伙食补贴、节日补贴、工会福利、计生补贴、体检等等);

3)可作为负责人申请博士后科学基金、国家自然科学基金及省、市各级课题;

4)出站留深工作满3年,符合深圳市后备级条件的可获160万元的住房补贴和可申请30万元RMB科研启动经费;

5)海外博士符合条件者可以申请深圳市孔雀计划160万住房补贴;

6)学校为每位博士后提供每两年2.5万元的学术交流资助。

 

科研助理待遇

1) 薪酬按学校相关规定定薪,月薪6000-13000元/月,视个人情况可向上浮动;

2) 大学规定的各种补助,年度考核奖金;

3) 落户深圳并帮助申请深圳市各类人才补助;

4) 有意攻读博士学位者也可先以研究助理身份加入课题组积累科研经验,之后可推荐攻读境内外博士生。

 

博士生硕士生招聘:

硕士生正常报考南科大本校学位点。(读硕期间生活补助:5万/年)

 

有意攻读博士学位的同学和科研人员,可选择本校博士学位,也可被推荐攻读联合培养博士生。联合培养学校包括以下著名/知名大学(香港科大、香港大学、新加坡国立、香港浸会大学、利兹大学、伯明翰大学、华威大学、东英吉利亚大学、澳门大学、美国天普大学等)。培养模式为2年国外/境外+2年南科大。本课题组目前主要的联合培养学校为澳门大学,香港科技大学和新加坡国立大学。博士学位为对方学校颁发。(读博期间生活补助:10万/年)

 

欢迎对混合/模拟/射频IC设计感兴趣的同学和科研人员加盟。同时欢迎来自国内外一流大学的访问学者和交流学生。

 

申请材料

详细的个人简历,含学习、工作和科研的经历,主要科研成果(如论文论著、成果证书或奖励),及其他可以证明工作能力的材料。(邮件标题注明:毕业学校+姓名+应聘职位)(本招聘信息长期有效)

欢迎有意者投简历到邮箱:panq@sustech.edu.cn

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