副教授 深港微电子学院

安丰伟博士于2019年加入南方科技大学,2013年在日本广岛大学获得工学博士学位。现在担任南方科技大学深港微电子学院副教授。在此之前担任过日本松下半导体公司的主管工程师及日本广岛大学副教授,其专长是图像识别与机器学习的大规模数字集成电路设计。积累了十年以上图像处理、图像识别、机器学习的电路设计和系统集成(SoC)等经验,具有丰富的学术界和工业界的背景。安教授在松下半导体公司开发的产品和在广岛大学的研究成果等的目标应用是高级辅助驾驶系统(ADAS)和自动驾驶。团队目前继续从事面向自动驾驶的动态目标追踪专用芯片的研究。

个人简介

研究领域

安丰伟博士的主要研究领域是基于计算机视觉的低功耗边缘人工智能芯片设计,具体包括图像处理、图像识别、机器学习的超大规模数字集成电路设计和系统集成,并有在工业界的研究开发经验。


教学

片上系统集成电路设计


学术成果 查看更多

1. Journal paper

[1] Guan, J., An, F., Zhang, X., Chen, L.,Mattausch, H. J., Energy-Efficient Hardware Implementation of Road-Lane Detection Based on Hough Transform with Parallelized Voting Procedure and Local Maximum Algorithm, IEICE Transaction on information systems, 2019.

[2] Luo, A.& An, F. & Zhang, X. & Mattausch, H.J., (2019). A Hardware-Efficient Recognition Accelerator Using Haar-Like Feature and SVM Classifier. IEEE Access. PP. 1-1. 10.1109/ACCESS.2019.2894169.

[3] An, F., Zhang, X., Luo, A., Chen, L., & Mattausch, H. J. , A Hardware Architecture for Cell-based Feature-Extraction and Classification Using Dual-Feature Space, IEEE Transactions on Circuits and Systems for Video Technology (TCSVT), DOI: 10.1109/TCSV2017.2726564, Jul. 13, 2017.

[4] Zhang, X., An, F., Chen, L., Ishii, I., & Mattausch, H. J., A Modular and Reconfigurable Pipeline Architecture for Learning Vector Quantization,IEEE transaction on circuits and system I: Regular papers (TCAS I), DOI: 10.1109/TCSI.2018.2804946, Feb. 23, 2018.

[5] Huang, Z., Zhang, X., Chen, L., Zhu, Y., An, F.*, Wang, H., & Feng, S., A Vector-Quantization Compression Circuit with On-Chip Learning Ability for High-Speed Image Sensor, IEEE Access, 5, 22132-22143, Oct. 17, 2017.

[6] Guan, J., An, F., Zhang, X., Chen, L., & Mattausch, H. J., (2017), Real-Time Straight-Line Detection for XGA-Size Videos by Hough Transform with Parallelized Voting Procedures, Sensors, 17(2), 270, Jan. 30, 2017.

[7] Huang, Z.,Suzuki, D., Zhang, X., Chen L., Zhu, Y., An, F., Wang, H., Feng, S., J. Mattausch, (2019). A Hardware-Efficient Vector Quantizer Based on Self-Organizing Map for High-Speed Image Compression. Appl. Sci. 2017, 7, 1106. Applied Sciences. 9. 1377. 10.3390/app9071377.

[8] Luo, A., An, F., Zhang, X., Chen, L., & Mattausch, H. J., Resource-Efficient Object-Recognition Coprocessor with Parallel Processing of Multiple Scan Windows in 65-nm CMOS, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 26(3), 431-444, Dec. 04, 2017.

[9] F.An, X. Zhang, L. Chen, and H.J. Mattausch, A Memory-based Modular Architecture for SOM and LVQ with Dynamic Configuration, IEEE Transactions on Multi-Scale Computing Systems (TMSCS), Vol.2 (4), pp. 234-241, 2016.

[10] Luo, A., An, F., Zhang, X., Chen, L., Huang, Z., Mattausch, H.J., (2018), Flexible feature-space-construction architecture and its VLSI implementation for multi-scale object detection, Japanese Journal of Applied Physics, 57(4S), 04FF04, Mar. 02, 2018.

[11] Zhang, X., An, F., Nakashima, I., Luo, A., Chen, L., Ishii, I., & Mattausch, H. J., A hardware-oriented histogram of oriented gradients algorithm and its VLSI implementation, Japanese Journal of Applied Physics, 56(4S), 04CF01, Jan. 30, 2017.

[12] Luo, A., An, F., Fujita, Y., Zhang, X., Chen, L., & Mattausch, H. J., (2017), Low-power coprocessor for Haar-like feature extraction with pixel-based pipelined architecture, Japanese Journal of Applied Physics, 56(4S), 04CF06, Mar. 07, 2017.

[13] An, F., K. Mihara, S. Yamasaki, L. Chen, and Mattausch, K-Nearest Neighbor Associative Memory with Reconfigurable Word-Parallel Architecture, Journal of Semiconductor Technology and Science, 16(4):405-414, Aug. 2016.

[14] An, F., K. Mihara, S. Yamasaki, L. Chen, and Mattausch, Highly flexible nearest-neighbor-search associative memory with integrated k nearest neighbor classifier, configurable parallelism and dual-storage space, Japanese Journal of Applied Physics, 55(4S):04EF10, April 2016.

[15] Zhang, An, F., L. Chen, and H.J. Mattausch, Reconfigurable VLSI implementation for learning vector quantization with on-chip learning circuit,Japanese Journal of Applied Physics, 55(4S):04EF02 April 2016.

[16] An, F., L. Chen, T. Akazawa, and H.J. Mattausch, k Nearest Neighbor Classification Coprocessor with Weighted Clock-Mapping-Based Searching, IEICE Transactions on Electronics, E99.C (3):397-403, March 2016.

[17] An, F., T. Akazawa, S. Yamasaki, L. Chen, and H. J. Mattausch, VLSI realization of learning vector quantization with hardware/software co-design for different applications. Japanese Journal of Applied Physics, vol.54, no.4s, pp. 4DE05, 2015.

[18] An, F. and H. J. Mattausch, K-means Clustering Algorithm for Multimedia Applications with Flexible HW/SW Co-design, Journal of System Architecture, (59), pp.155-164, 2013.

[19] I.Wicaksono, F. An, and H.J. Mattausch, Memory Based Hardware-Accelerated System for High-Speed Human Recognition, Advanced Robotics, 28 (5), pp.317-327, 2014.

[20] F.An, T. Koide, and H. J. Mattausch, A K-means-based Multi-Prototype High-Speed Learning System with FPGA-implemented Coprocessor for 1-NN Searching, IEICE Transaction on information systems, Vol. E95-D, No.9, 2327-2338, 2012.

[21]An, F., Multi-port SRAM with Multi-bank for Self-organizing Maps Neural Network, IEEE International Conference on Solid-state and Integrated Circuit Technology, Oct. 2018. (Invited)

[22] An, F., Zhang, X., Chen, L. & Ishii, I., Object-recognition VLSI for pedestrian detection in automotive applications. In IEEE 12th International Conference on ASIC (ASICON), China, Guiyang, Oct., pp. 651-653. 2017. (Invited)

[23] An, F., Zhang, X., Chen, L., & Mattausch, H. J., “Dynamically Reconfigurable System for LVQ-based On-Chip Learning and Recognition,” In IEEE International Symposium on Circuits and Systems (ISCAS), Canada, Montreal, May, pp. 1338-1341, 2016.

[24] An, F., X. Zhang, L. Chen, and H.J. Mattausch, Parallel-Elementary-Stream Architecture for Nearest-Neighbor-Search-based Self-Organizing Map, IEEE International Conference on Solid-state and Integrated Circuit Technology, Oct. 2016. (Invited)

[25] Pang, H. Huang, An, F., and H. Yu, Low-power and Real-time Computer Vision On-chip, in13thIEEE International SoC design Conference, South Korea, Jeju, Oct. 2016. (Invited)

[26] An, F., T. Akazawa, S. Yamasaki, L. Chen, and H. J. Mattausch, Word-parallel Associative Memory for k-Nearest-Neighbor with Configurable Storage Space of Reference Vectors, IEEE Asian Solid-State Circuits Conference (ASSCC), China, Xiamen, pp. 1-4, 2015.

[27] An, F., T. Akazawa, S. Yamazaki, L. Chen, and H.J. Mattausch, A Coprocessor for Nearest Clock-based Euclidean Distance Search towards multiple applications, IEEE Custom Integrated Circuits Conference (CICC), USA, California, pp. 1-6, 2014.

3. Issued Patent

An, F., Mattausch, H. J., Chen, L., Zhang, X., & Luo, A.,Image recognition device, Application No: JP2017-030253.

新闻动态 更多新闻

  • 南方科技大学安丰伟教授做客华中科技大学光电信息学术讲座

    2019-10-30
  • 中国石油大学邀请安丰伟副教授做客“名师有约”学术论坛

    2019-10-30

团队成员 查看更多

加入团队

南方科技大学深港微电子学院安丰伟课题组招聘博士后2名

研究方向:图像处理,图像识别,人工智能,硬件设计,集成电路。

任职资格:(1)年龄不超过35岁,取得图像处理,图像识别,人工智能,硬件设计,集成电路等相关研究方向的全日制博士学位的海内外优秀博士;

         (2)精通Verilog HDL和C语言;

         (3)具有较强的科研和创新能力,良好的团队合作精神,事业心强,诚实守信,身体健康。

课题组PI简介

     安丰伟博士现为南方科技大学深港微电子学院副教授,主要研究领域是基于计算机视觉的低功耗边缘人工智能芯片设计,具体包括图像处理、图像识别、机器学习的超大规模数字集成电路设计和系统集成,并有在工业界的研究开发经验。

个人主页:https://sme.sustech.edu.cn/index/teacher/neiye/id/35.html

待遇

  1. 岗位聘期两年,年薪不低于30万元。享受五险一金、住房补贴、过节费、餐补,免费体检等福利待遇;*条件优秀者还可申请校长卓越奖励计划。
  2. 学校为每位博士后提供5万元的学术交流资助。
  3. 博士后出站后可申请深圳市的30万元出站科研资助;如果留深工作,符合条件者可获得深圳市高层次人才购房补贴160-200万元;如果成功申请到广东省特支计划再加50万个人补贴。

课题组优势

    课题组为各位前来工作的学生学者提供良好的科研环境,课题组研究经费充裕,组内各研究方向人员保持良性互动,拥有良好的学术氛围,课题组提供良好的科研条件,鼓励并协助博士后研究人员申报国家自然科学基金、中国博士后科学基金、广东省博士后科研资助项目等。表现优秀者课题组会为其提供国内外知名高校,科研院所的相应推荐,为其未来的发展打下坚实的基础。

    有意应聘者请将详细简历发送至以下邮箱:anfw@sustech.edu.cn,初步确认意向后,我们会邀请候选人来校访问面谈。

南方科技大学安丰伟课题组FPGA工程师招聘

一、招聘要求:

    1、学历本科及以上,本科需3年以上FPGA芯片开发经验,硕士可适当放低工作经验要求;

    2、熟练使用verilog语言、EDA软件工具,熟悉Xilinx/Altera FPGA

二、岗位职责:

    1.FPGA电路设计,代码编写,仿真和调试,以及相关的硬件调试。

    2.FPGA的主要应用领域:数字IC验证,各种接口电路设计,及其它功能模块。

三、岗位待遇:
    1、提供有竞争力的薪酬待遇;享受按国家法定节假日及按学校规定的带薪年假。
    2、良好的个人成长与发展空间。
    3、按国家相关规定缴纳五险一金。
    4、享受过节费、餐补、计划生育奖励、定期体检等福利待遇。

四、应聘方式:

    有意应聘者请将个人简历发至邮箱anfw@sustech.edu.cn,邮件标题请标明:FPGA工程师应聘+本人姓名。初步确认意向后,我们会邀请候选人来学校访问面谈。我们在美丽的南科大诚邀您的加入!

PI简介:

    安丰伟, 南方科技大学深港微电子学院副教授,主要研究领域是基于计算机视觉的低功耗边缘人工智能芯片设计,具体包括图像处理、图像识别、机器学习的超大规模数字集成电路设计和系统集成,并有在工业界的研究开发经验.

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联系地址

广东省深圳市南山区南方科技大学第二科研楼329

办公电话

0755-88015992

电子邮箱

anfw@sustech.edu.cn

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