Jian Yang

2018-09-30

Education

 

Southeast University                              Nanjing, China 2014-2017

M.Eng., Microelectronics & Solid State Electronics

National ASIC Engineering Technology Research Center

School of Electronics Science & Engineering

 


Hubei University                                       Wuhan, China 2010-2014

B.Eng., Microelectronics

College of Physics & Electronic Technology

Journal Papers

Published Research

(1) Jian Yang, Jianhui Wu, and Chao Chen. “The design of a limit amplifier in a low
voltage.” Southeast University Graduate Symposium, 2017.

(2) Chunfeng Bai, Jian Yang, and Jianhui Wu. “A highly linear programmable gain amplifier with
level shifter and class AB output stage for Bluetooth low energy”, Asia-Pacific Microwave Conference (APMC). IEEE, 2015:1-3.

Research

Relevant Research Experience and Employment

Analog Integrated Circuit Engineer @Sanechips (ZTE), Shenzhen           Jul., 2017- Jul., 2018

  • Circuit design of TX block in high speed Serdes circuit, including P2S, Driver and IO
    (HSTL).
  • Simulation, optimization, layout guidance of above circuit.
  • Chip test and establish technical documents.
  • Writing IP technical documents.

Circuit and layout designer @Southeast University (ASIC), Nanjing           Nov., 2015-Mar. 2017

  • Circuit design of VGA block in low power GPS receiver.
  • Schematic establishment, simulation, optimization, layout design of above circuit.
  • Chip test and documents.

Circuit and layout designer @Southeast University (ASIC), Nanjing.         Jun., 2015-Mar. 2016

  • Circuit design of VGA block in low power Bluetooth receiver.
  • Schematic establishment, simulation, optimization, layout design of above circuit.
  • Chip test and documents.

Circuit and layout designer @Southeast University (ASIC), Nanjing.           Feb., 2015-Jun. 2015

  • Circuit design of VGA block in 433MHz RF receiver.
  • Simulation, optimization, layout design of above circuit.
  • Chip test and documents.