- Journal Papers
- Journal Papers
- Authored Books

1.X. Lou, P. K. Meher,** Y. J. Yu** and W. B. Ye, “Novel Structure for Area-Energy-Efficient Implementation of FIR Filter”, accepted by IEEE Transactions on Circuits and Systems II,Oct,2017.

2.W. B. Ye, X. Lou, and **Y. J. Yu**, “Design of Low Power Multiplierless Linear-Phase FIR Filters”, Accepted by IEEE Access,Aug,2017.

3.X. Lou, **Y. J. Yu** and P. K. Meher, “Lower Bound Analysis and Perturbation of Critical Path for Area-Time Efficient Multiple Constant Multiplications”, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 2, pp. 313 – 324, Feb. 2017.

4.X. Lou, **Y. J. Yu** and P. K. Meher, “Analysis and Optimization of Product-Accumulation Section for Efficient Implementation of FIR Filters”, IEEE Trans. Circuits, Syst. I, vol. 63, no. 10, pp. 1701 – 1703, Oct. 2016

5.R. Fan, **Y. J. Yu** and Y. L. Guan, “Improved Orthogonal Frequency Division Multiplexing with Generalized Index Modulation”, IET Communications, vol. 10, iss. 8, pp. 969-974, Aug. 2016.

6.W. B. Ye and **Y. J. Yu**, “Greedy Algorithm for the Design of Linear-Phase FIR Filter with Sparse Coefficients”, Circuits Systems and Signal Processing, vol. 35, no. 4, pp. 1427-1436, April 2016.

7.X. Lou, **Y. J. Yu** and P. K. Meher, “New Approach to the Reduction of Sign-extension Overhead for Efficient Implementation of Multiple Constant Multiplications”, IEEE Trans. Circuits, Syst. I., vol. 62, no. 11, pp. 2695-2705, Nov. 2015.

8.R. Fan, **Y. J. Yu** and Y. L. Guan, “Generalization of Orthogonal Frequency Division Multiplexing with Index Modulation”, IEEE Trans. Wireless Communications, vol. 14, no. 10, pp. 5350-5359, Oct. 2015.

9.W. B. Ye and **Y. J. Yu**, “Two-step Optimization Approach for the Design of Multiplierless Linear-Phase FIR Filters”, IEEE Trans. Circuits, Syst. I., vol. 62, no. 5, pp. 1279-1287, May 2015. (Invited paper for special issue of IEEE TCAS-I on best papers selected from ISCAS’14.)

10.X. Lou, **Y. J. Yu** and P. K. Meher, “Fine-Grained Critical Path Analysis and Optimization for Area-Time Efficient Realization of Multiple Constant Multiplications”, IEEE Trans. Circuits, Syst. I., vol. 62, no. 3, pp. 863-872, March 2015.

11.W. B. Ye, and **Y. J. Yu**, “Bit-level Multiplierless FIR Filter Optimization Incorporating Sparse Filter Technique”, IEEE Trans. Circuits, Syst. I., vol. 61, no. 11, pp. 3206-3215, Nov. 2014.

12.W. J. Xu, **Y. J. Yu**, and H. Johansson, “Improved Filter Bank Approach for the Design of Variable Bandedge and Fractional Delay Filters”, IEEE Trans. Circuits, Syst. I., vol. 61, no. 3, pp. 764-777, March 2014.

13.W. B. Ye, and **Y. J. Yu**, “Single Stage and Cascade Design of High Order Multiplierless linear phase FIR Filters Using Genetic Algorithm”, IEEE Trans. Circuits, Syst. I., vol. 60, no. 11, pp. 2987-2997, Nov. 2013. (Invited paper for special issue of IEEE TCAS-I on best papers selected from ISCAS’12.)

14.**Y. J. Yu**, and W. J. Xu, “Investigation on the Optimization Criteria for the Design of Variable Fractional Delay Filters”, IEEE Trans. Circuits, Syst. II., vol. 60, no. 8, pp. 522-526, Aug. 2013.

15.S. Y. Park, and **Y. J. Yu**, “Fixed-Point Analysis and Parameter Selections of MSR-CORDIC with Applications to FFT Designs”, IEEE Trans. Signal Processing, vol. 60, no. 12, pp.6245-6256, Dec. 2012.

16.**Y. J. Yu**, and W. J. Xu, “Mixed-Radix Fast Filter Bank Approach for the Design of Variable Digital Filters with Simultaneously Tunable Bandedge and Fractional Delay”, IEEE Trans. Signal Processing, vol. 60, no. 1, pp.100-111, Jan. 2012.

17.D. Shi, and **Y. J. Yu**, “Design of Discrete-valued Linear Phase FIR Filters in Cascade Form”, IEEE Trans. Circuits, Syst. I. vol. 58, no. 7, pp.1627-1636, July 2011. (Invited paper for special issue of IEEE TCAS-I on best papers selected from ISCAS’10.)

18.R. Bregovic, **Y. J. Yu**, T. Saramäki, and Y. C. Lim, “Implementation of Linear-Phase FIR Filters for a Rational Sampling Rate Conversion Utilizing the Coefficient Symmetry”, IEEE Trans. Circuits, Syst. I. vol. 58, no. 3, pp. 548-561, Mar. 2011.

19.D. Shi, and **Y. J. Yu**, “Design of Linear Phase FIR Filters with High Probability of Achieving Minimum Number of Adders”, IEEE Trans. Circuits, Syst. I. vol. 58, no. 1, pp. 126-136, Jan. 2011.

20.R. Bregovic, **Y. J. Yu**, A. Viholainen and Y. C. Lim, “Implementation of Linear-Phase FIR Nearly Perfect-Reconstruction Cosine-Modulated Filterbanks Utilizing the Coefficient Symmetry”, IEEE Trans. Circuits, Syst. I. vol. 57, no. 1, pp. 139-151, Jan. 2010.

21.Y. Lian and **Y. J. Yu**, “Guest Editorial: Low-Power Digital Filter Design Techniques and Their Applications”, Circuit Syst. Signal Process, vol. 29, no. 1, pp. 1-5, Jan. 2010.

22.**Y. J. Yu**, and Y. C. Lim, “Optimization of Linear Phase FIR Filters in Dynamically Expanding Subexpression Space”, Circuit Syst. Signal Process, vol. 29, no. 1, pp. 65-80, Feb. 2010.

23.**Y. J. Yu,** D. Shi, and Y. C. Lim, “Design of Extrapolated Impulse Response FIR Filters with Residual Compensation in Subexpression Space”, IEEE Trans. Circuits, Syst. I, vol. 56, no. 12, pp. 2621-2633, Dec. 2009.

24.**Y. J. Yu**, Y. C. Lim and D. Shi, “Low Complexity Design of Variable Bandedge Linear Phase FIR filters with Sharp Transition Band”, IEEE Trans. Signal Processing, vol. 57, no. 4, pp. 1328-1338, April 2009.

25.**Y. J. Yu** and Y. C. Lim, “Design of Linear Phase FIR Filters in Subexpression Space Using Mixed Integer Linear Programming”, IEEE Trans. Circuits, Syst. I, vol. 54, no. 10, pp. 2330-2338, Oct. 2007.

26.Y. C. Lim, **Y. J. Yu**, T. Saramäki and K. L. Teo, "FRM Based FIR Filters with Optimum Finite Word Length Performance," IEEE Trans. Signal Processing, vol. 55, pp. 2914-2924, June 2007.

27.**Y. J. Yu** and Y. C. Lim, "Roundoff Noise Analysis of Signals Represented Using Signed Power-of-Two Terms," ?IEEE Trans. Signal Processing, vol. 55, pp. 2122-2135, May 2007.

28.**Y. J. Yu**, Y. C. Lim and T. Saram?ki, “Restoring Coefficient Symmetry in Polyphase Implementation of Linear Phase FIR filters”, Circuit Syst. Signal Process., vol. 25, pp. 253-264, Apr 2006.

29.Y. C. Lim, **Y. J. Yu** and T. Saram?ki, “Optimum masking levels and coefficient sparseness for Hilbert transformers and half-band filters designed using the frequency-response masking technique,” IEEE Trans. Circuits, Syst. I, vol 52, no. 11, pp. 2444-2453, Nov 2005.

30.Y. C. Lim and **Y. J. Yu**, “Synthesis of Very Sharp Hilbert Transformer Using the Frequency-Response Masking Technique,” IEEE Trans. Signal Process., vol. 53, no. 7, pp. 2595-2597, July 2005.

31.**Y. J. Yu**, K. L. Teo, Y. C. Lim, and G. H. Zhao., “Extrapolated Impulse Response Filter and its Application in the Synthesis of Digital Filters Using the Frequency-Response Masking Technique,” Signal Processing (Elsevier), Vol 85/3 pp. 581-590, March 2005.

32.Y. C. Lim and **Y. J. Yu**, “A width-recursive depth-first tree search approach for the design of discrete coefficient perfect reconstruction lattice filter bank,” IEEE Trans. Circuits, Syst. II, vol. 50, pp. 257-266, June 2003.

33.Y. C. Lim, **Y. J. Yu**, H. Q. Zheng and S. W. Foo, “FPGA implementation of digital filters synthesized using the FRM technique,” Circuit Syst. Signal Process., vol. 22, pp. 211-218, March 2003.

34.Y. C. Lim, Y. Sun and **Y. J. Yu**, “Design of discrete-coefficient FIR filters on loosely connected parallel machines”, IEEE Trans. Signal Processing,vol. 50, pp. 1409 - 1416, June 2002.

35.**Y. J. Yu** and Y. C. Lim, “A novel genetic algorithm for the design of a signed power-of-two coefficient quadrature mirror filter lattice filter bank”, Circuit Syst. Signal Process., vol. 21, pp. 263-276, May 2002.

1.X. Lou, W. B. Ye, and **Y. J. Yu**, “Investigation on Power Consumption of Product Accumulation Block For Multiplierless FIR Filters”, in Proceedings of the 2017 International Conference on Digital Signal Processing (DSP), London, UK, Aug. 2017.

2.W. L. Chen, **Y. J. Yu** and H. J. Shi, “An Improvement of Edge-Adaptive Image Scaling Algorithm Based on Sobel Operator”, in Proceedings of the 4th International Conference on Information Science and Control Engineering (ICISCE 2017), Changsha, China, July 2017.

3.**Y. J. Yu**, Z. Yang, B.-S. Oh, Y. K. Yeo, G.-B. Huang and Z. Lin, “Investigation on Driver Stress Utilizing ECG signals with On-board Navigation Systems in Use”, in Proceedings of the 2016 International Conference on Control, Automation, Robotics and Vision (ICARCV2016), Phuket, Thailand, Nov. 2016.

4.W. B. Ye and **Y. J. Yu**, “An Efficient FIR Filtering Technique for Processing Non-uniformly Sampled Signal”, in Proceedings of the 2015 IEEE International Conference on Digital Signal Processing (DSP), Singapore, July 2015.

5.X. Lou and **Y. J. Yu**, “Area-Time Efficient Realization of Multiple Constant Multiplication”, in Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, Lisbon, Portugal, May 2015.

6.W. B. Ye, X. Lou and **Y. J. Yu**, “On the Design of High-Speed Multiplierless Linear-Phase FIR Filters”, in Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, Lisbon, Portugal, May 2015.

7.X. Lou, P. K. Meher, **Y. J. Yu**, “Fine-Grained Pipelining for Multiple Constant Multiplications”, in Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, Lisbon, Portugal, May 2015.

8.R. Fan, **Y. J. Yu** and Y. L. Guan, “Orthogonal Frequency Division Multiplexing with Generalized Index Modulation”, in Proceeding of GlobeCom 2014, Austin, TX.

9.W. B. Ye and **Y. J. Yu**, “A Polynomial-Time Algorithm for the Design of Multiplierless Linear-Phase FIR Filters with Low Hardware Cost”, in Proceedings of the 2014 IEEE International Symposium on Circuits and Systems, Melbourne, Australia, June 2014.

10.X. Lou, **Y. J. Yu** and P. K. Meher, “High-Speed Multiplier Block Design Based on Bit-Level Critical Path Optimization”, in Proceedings of the 2014 IEEE International Symposium on Circuits and Systems, Melbourne, Australia, June 2014.

11.H. Zhao, W. B. Ye and** Y. J. Yu**, “Sparse FIR Filter Design Based on Genetic Algorithm”, in Proceedings of the 2013 IEEE International Symposium on Circuits and Systems, Beijing, PRChina, May 2013.

12.W. B. Ye and **Y. J. Yu**, “Design of high order and wide coefficient wordlength multiplierless FIR filters with low hardware cost using genetic algorithm”, in Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, Seoul, South Korea, May 2012.

13.W. B. Ye and **Y. J. Yu**, “An Algorithm for the Design of Low Power Linear Phase FIR Filters”, in Proceedings of the 2011 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics, Macau, China, Oct. 2011. (Silver Leaf Certificate)

14.**Y. J. Yu**, “Design of Variable Bandedge FIR Filters with Extremely Large Bandedge Variation Range”, in Proceedings of the 2011 IEEE International Symposium on Circuits and Systems, Rio de Janeiro, Brazil, May 2011.

15.W. B. Ye and** Y. J. Yu**, “Switching Activity Analysis and Power Estimation for Multiple Constant Multiplier Block of FIR Filters”, in Proceedings of the 2011 IEEE International Symposium on Circuits and Systems, Rio de Janeiro, Brazil, May 2011.

16.D. Shi and **Y. J. Yu**, “Low-Complexity Linear Phase FIR Filters in Cascade Form”, in Proceedings of the 2010 IEEE International Symposium on Circuits and Systems, Paris, France, May 2010.

17.W. J. Xu and **Y. J. Yu**, “Polynomial Implementation Structure for Lagrange-Type Variable Fractional Delay Filters”, in Proceedings of the 2010 IEEE International Symposium on Circuits and Systems, Paris, France, May 2010.

18.P. Sun, G. Wang, W. Woods, H. Wang and **Y. J. Yu**, “An adaptive body-bias low voltage low power LC VCO”, in Proceedings of the 2010 IEEE International Symposium on Circuits and Systems, Paris, France, May 2010.

19.S. Y. Park and** Y. J. Yu**, “An Improved Structure and Design Procedure for Signed Power-of-two Lattice QMF Bank”, in Proc. 2009 International Symposium on Integrated Circuits (ISIC 2009), Singapore, Dec. 2009.

20.**Y. J. Yu** and Y. C. Lim, “Optimization of FIR Filters in Subexpression Space with Constrained Adder Depth”, in 6th International Symposium on Image and Signal Processing and Analysis (ISPA 2009), Salzburg, Austria, Sept. 2009.

21.**Y. J. Yu**, D. Shi and R. Bregovic, “On the Complexity Reduction of Polyphase Linear Phase FIR Filters with Symmetric Coefficient Implementation”, in Proceedings of the 2009 IEEE International Symposium on Circuits and Systems, Taipei, Taiwan, May 2009.

22.**Y. J. Yu**, D. Shi and Y. C. Lim, “Subexpression Encoded Extrapolated Impulse Response FIR Filter with Perfect Residual Compensation”, in Proceedings of the 2008 IEEE International Symposium on Circuits and System., Seattle, WA, May 2008.

23.**Y. J. Yu** and Y. C. Lim, "Roundoff Noise Analysis for FSK Signals in White Noise Represented as Signed Power-of-Two Numbers," in Proc. 2007 International Conference on Electronics, Circuits and Systems, Marrakech, Morocco, pp. 796-799. Dec 2007.

24.Y. C. Lim, **Y. J. Yu**, T. Saramäki and K. L. Teo, “FRM-Based FIR Filters with Minimum Coefficient Sensitivities”, in Proc. 2007 IEEE International Symposium on Circuits and Systems,

New Orleans, LA, May 2007.

25.Y. C. Lim,** Y. J. Yu**, T. Saramäki, “FRM approach for hubert transformer synthesis”, in Proc. 4th International Conference on Information Technology and Applications, ICITA 2007, Harbin, China, Jan. 2007.

26.**Y. J. Yu** and Y. C. Lim, "Roundoff Noise Analysis of Signals Represented Using Signed Power-of-Two Terms," in Proc. 14th European Signal Processing Conference EUSIPCO2006, Florence, Italy, Sept. 2006.

27.R. Bregovic, T. Saramäki, **Y. J. Yu**, Y. C. Lim, “An Efficient Implementation of Linear-Phase Fir Filters for a Rational Sampling Rate Conversion”, in Proceedings of the 2006 IEEE International Symposium on Circuits and Systems, pp. 5395-5398. Island of Kos, Greece, May 2006.

28.**Y. J. Yu**, Y. C. Lim, “Signed Power-of-Two Allocation Scheme for the Design of Lattice Orthogonal Filter Banks”, in Proceedings of the 2005 IEEE International Symposium on Circuits and Systems, pp. 1819-1822. Kobe, Japan, May 2005.

29.**Y. J. Yu**, Y. C. Lim, K. L. Teo and G. H. Zhao, "Frequency-Response Masking Technique Incorporating Extrapolated Impulse Response Band-edge Shaping Filter", in Proceedings of the 2004 IEEE International Symposium on Circuits and Systems, vol. 5. pp. 532-535. Vancouver, Canada, May 2004.

30.J. Yli-Kaakinen, T. Saramäki and **Y. J. Yu**, "An Efficient Algorithm for the Optimization of FIR Filters Synthesized Using the Multistage Frequency-Response Masking Approach", in Proceedings of the 2004 IEEE International Symposium on Circuits and Systems, vol. 5. pp. 540-543. Vancouver, Canada, May 2004.

31.**Y. J. Yu**, G. H. Zhao, K. L. Teo and Y. C. Lim, “Optimization of Extrapolated Impulse Response Filters Using Semi-Infinite Programming”, in Proceedings of 2004 First International Symposium on Control, Communications and Signal Processing, ICCSSP04, pp. 397 – 400, Hammamet, Tunisia, March 2004.

32.**Y. J. Yu**, G. H. Zhao, K. L. Teo and Y. C. Lim, "Optimization and Implementation of Extrapolated Impulse Response Filters", in Proceedings of 2003 IEEE Conf. Neural Network & Signal Processing, pp. 744-747. Nanjing, China, Dec. 2003.

33.**Y. J. Yu**,T. Saramäki and Y. C. Lim, "An iterative method for optimizing FIR filters synthesized using the two-stage frequency-response masking technique", in Proceedings of the 2003 IEEE International Symposium on Circuits and Systems,. Vol. 3. pp. 874 - 877. Bangkok, Thailand, 25-28 May 2003.

34.**Y. J. Yu** and Y. C. Lim, "Genetic algorithm approach for the optimization of multiplierless sub-filters generated by the frequency-response masking technique", in Proceedings of the 2002 IEEE International Conference on Electronics Computers and Systems, Vol. 3,pp. 1163 - 1166, Dubrovnik, Croatia, 15-18 Sept., 2002.

35.**Y. J. Yu** and Y. C. Lim, "FRM based FIR filter design - the WLS approach", in Proceedings of the 2002 IEEE International Symposium on Circuits and Systems,. Vol. 3. pp. 221 - 224. Phoenix, AZ, 26-29 May 2002.

36.**Y. J. Yu** and Y. C. Lim, "New natural selection process and chromosome encoding for the design of multiplierless lattice QMF using genetic algorithm", in Proceedings of the 2001 IEEE International Conference on Electronics Computers and Systems, Vol. 3, pp. 1273 - 1276. Malta, 2-5 Sept. 2001.

37.**Y. J. Yu** and Y. C. Lim, "A sequential reoptimization approach for the design of signed power-of-two coefficient lattice QMF bank", in Proceedings of the 2001 IEEE Region 10 International Conference on Electrical and Electronic Technology. Vol. 1, pp. 57 - 60. Singapore, 19-22 Aug. 2001.

38.Y. C. Lim, **Y. J. Yu**, H. Q. Zheng and S. W. Foo, "FPGA implementation of digital filters synthesized using the frequency-response masking technique", in Proceedings of the 2001 IEEE International Symposium on Circuits and Systems,.Vol. 2, pp. 173 - 176. Sydney, Australia, 6-9 May 2001.

39.Y. C. Lim and **Y. J. Yu**, "A successive reoptimization approach for the design of discrete coefficient perfect reconstruction lattice filter bank", in Proceedings of the 2000 IEEE International Symposium on Circuits and Systems,. Vol. 2.pp. 69 - 72.28-31, Geneva, Switzerland, May 2000.

**Digital Filter Structures and Their Implementation**

* Academic Press Library in Signal Processing: Volume 1: Signal Processing Theory and Machine Learning*, (Editor-in-Chief: Sergios Theodoridis and Rama Chellappa, Publisher: Academic Press), 2013.

1.X. Lou, P. K. Meher,** Y. J. Yu** and W. B. Ye, “Novel Structure for Area-Energy-Efficient Implementation of FIR Filter”, accepted by IEEE Transactions on Circuits and Systems II,Oct,2017.

2.W. B. Ye, X. Lou, and **Y. J. Yu**, “Design of Low Power Multiplierless Linear-Phase FIR Filters”, Accepted by IEEE Access,Aug,2017.

3.X. Lou, **Y. J. Yu** and P. K. Meher, “Lower Bound Analysis and Perturbation of Critical Path for Area-Time Efficient Multiple Constant Multiplications”, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 2, pp. 313 – 324, Feb. 2017.

4.X. Lou, **Y. J. Yu** and P. K. Meher, “Analysis and Optimization of Product-Accumulation Section for Efficient Implementation of FIR Filters”, IEEE Trans. Circuits, Syst. I, vol. 63, no. 10, pp. 1701 – 1703, Oct. 2016

5.R. Fan, **Y. J. Yu** and Y. L. Guan, “Improved Orthogonal Frequency Division Multiplexing with Generalized Index Modulation”, IET Communications, vol. 10, iss. 8, pp. 969-974, Aug. 2016.

6.W. B. Ye and **Y. J. Yu**, “Greedy Algorithm for the Design of Linear-Phase FIR Filter with Sparse Coefficients”, Circuits Systems and Signal Processing, vol. 35, no. 4, pp. 1427-1436, April 2016.

7.X. Lou, **Y. J. Yu** and P. K. Meher, “New Approach to the Reduction of Sign-extension Overhead for Efficient Implementation of Multiple Constant Multiplications”, IEEE Trans. Circuits, Syst. I., vol. 62, no. 11, pp. 2695-2705, Nov. 2015.

8.R. Fan, **Y. J. Yu** and Y. L. Guan, “Generalization of Orthogonal Frequency Division Multiplexing with Index Modulation”, IEEE Trans. Wireless Communications, vol. 14, no. 10, pp. 5350-5359, Oct. 2015.

9.W. B. Ye and **Y. J. Yu**, “Two-step Optimization Approach for the Design of Multiplierless Linear-Phase FIR Filters”, IEEE Trans. Circuits, Syst. I., vol. 62, no. 5, pp. 1279-1287, May 2015. (Invited paper for special issue of IEEE TCAS-I on best papers selected from ISCAS’14.)

10.X. Lou, **Y. J. Yu** and P. K. Meher, “Fine-Grained Critical Path Analysis and Optimization for Area-Time Efficient Realization of Multiple Constant Multiplications”, IEEE Trans. Circuits, Syst. I., vol. 62, no. 3, pp. 863-872, March 2015.

11.W. B. Ye, and **Y. J. Yu**, “Bit-level Multiplierless FIR Filter Optimization Incorporating Sparse Filter Technique”, IEEE Trans. Circuits, Syst. I., vol. 61, no. 11, pp. 3206-3215, Nov. 2014.

12.W. J. Xu, **Y. J. Yu**, and H. Johansson, “Improved Filter Bank Approach for the Design of Variable Bandedge and Fractional Delay Filters”, IEEE Trans. Circuits, Syst. I., vol. 61, no. 3, pp. 764-777, March 2014.

13.W. B. Ye, and **Y. J. Yu**, “Single Stage and Cascade Design of High Order Multiplierless linear phase FIR Filters Using Genetic Algorithm”, IEEE Trans. Circuits, Syst. I., vol. 60, no. 11, pp. 2987-2997, Nov. 2013. (Invited paper for special issue of IEEE TCAS-I on best papers selected from ISCAS’12.)

14.**Y. J. Yu**, and W. J. Xu, “Investigation on the Optimization Criteria for the Design of Variable Fractional Delay Filters”, IEEE Trans. Circuits, Syst. II., vol. 60, no. 8, pp. 522-526, Aug. 2013.

15.S. Y. Park, and **Y. J. Yu**, “Fixed-Point Analysis and Parameter Selections of MSR-CORDIC with Applications to FFT Designs”, IEEE Trans. Signal Processing, vol. 60, no. 12, pp.6245-6256, Dec. 2012.

16.**Y. J. Yu**, and W. J. Xu, “Mixed-Radix Fast Filter Bank Approach for the Design of Variable Digital Filters with Simultaneously Tunable Bandedge and Fractional Delay”, IEEE Trans. Signal Processing, vol. 60, no. 1, pp.100-111, Jan. 2012.

17.D. Shi, and **Y. J. Yu**, “Design of Discrete-valued Linear Phase FIR Filters in Cascade Form”, IEEE Trans. Circuits, Syst. I. vol. 58, no. 7, pp.1627-1636, July 2011. (Invited paper for special issue of IEEE TCAS-I on best papers selected from ISCAS’10.)

18.R. Bregovic, **Y. J. Yu**, T. Saramäki, and Y. C. Lim, “Implementation of Linear-Phase FIR Filters for a Rational Sampling Rate Conversion Utilizing the Coefficient Symmetry”, IEEE Trans. Circuits, Syst. I. vol. 58, no. 3, pp. 548-561, Mar. 2011.

19.D. Shi, and **Y. J. Yu**, “Design of Linear Phase FIR Filters with High Probability of Achieving Minimum Number of Adders”, IEEE Trans. Circuits, Syst. I. vol. 58, no. 1, pp. 126-136, Jan. 2011.

20.R. Bregovic, **Y. J. Yu**, A. Viholainen and Y. C. Lim, “Implementation of Linear-Phase FIR Nearly Perfect-Reconstruction Cosine-Modulated Filterbanks Utilizing the Coefficient Symmetry”, IEEE Trans. Circuits, Syst. I. vol. 57, no. 1, pp. 139-151, Jan. 2010.

21.Y. Lian and **Y. J. Yu**, “Guest Editorial: Low-Power Digital Filter Design Techniques and Their Applications”, Circuit Syst. Signal Process, vol. 29, no. 1, pp. 1-5, Jan. 2010.

22.**Y. J. Yu**, and Y. C. Lim, “Optimization of Linear Phase FIR Filters in Dynamically Expanding Subexpression Space”, Circuit Syst. Signal Process, vol. 29, no. 1, pp. 65-80, Feb. 2010.

23.**Y. J. Yu,** D. Shi, and Y. C. Lim, “Design of Extrapolated Impulse Response FIR Filters with Residual Compensation in Subexpression Space”, IEEE Trans. Circuits, Syst. I, vol. 56, no. 12, pp. 2621-2633, Dec. 2009.

24.**Y. J. Yu**, Y. C. Lim and D. Shi, “Low Complexity Design of Variable Bandedge Linear Phase FIR filters with Sharp Transition Band”, IEEE Trans. Signal Processing, vol. 57, no. 4, pp. 1328-1338, April 2009.

25.**Y. J. Yu** and Y. C. Lim, “Design of Linear Phase FIR Filters in Subexpression Space Using Mixed Integer Linear Programming”, IEEE Trans. Circuits, Syst. I, vol. 54, no. 10, pp. 2330-2338, Oct. 2007.

26.Y. C. Lim, **Y. J. Yu**, T. Saramäki and K. L. Teo, "FRM Based FIR Filters with Optimum Finite Word Length Performance," IEEE Trans. Signal Processing, vol. 55, pp. 2914-2924, June 2007.

27.**Y. J. Yu** and Y. C. Lim, "Roundoff Noise Analysis of Signals Represented Using Signed Power-of-Two Terms," ?IEEE Trans. Signal Processing, vol. 55, pp. 2122-2135, May 2007.

28.**Y. J. Yu**, Y. C. Lim and T. Saram?ki, “Restoring Coefficient Symmetry in Polyphase Implementation of Linear Phase FIR filters”, Circuit Syst. Signal Process., vol. 25, pp. 253-264, Apr 2006.

29.Y. C. Lim, **Y. J. Yu** and T. Saram?ki, “Optimum masking levels and coefficient sparseness for Hilbert transformers and half-band filters designed using the frequency-response masking technique,” IEEE Trans. Circuits, Syst. I, vol 52, no. 11, pp. 2444-2453, Nov 2005.

30.Y. C. Lim and **Y. J. Yu**, “Synthesis of Very Sharp Hilbert Transformer Using the Frequency-Response Masking Technique,” IEEE Trans. Signal Process., vol. 53, no. 7, pp. 2595-2597, July 2005.

31.**Y. J. Yu**, K. L. Teo, Y. C. Lim, and G. H. Zhao., “Extrapolated Impulse Response Filter and its Application in the Synthesis of Digital Filters Using the Frequency-Response Masking Technique,” Signal Processing (Elsevier), Vol 85/3 pp. 581-590, March 2005.

32.Y. C. Lim and **Y. J. Yu**, “A width-recursive depth-first tree search approach for the design of discrete coefficient perfect reconstruction lattice filter bank,” IEEE Trans. Circuits, Syst. II, vol. 50, pp. 257-266, June 2003.

33.Y. C. Lim, **Y. J. Yu**, H. Q. Zheng and S. W. Foo, “FPGA implementation of digital filters synthesized using the FRM technique,” Circuit Syst. Signal Process., vol. 22, pp. 211-218, March 2003.

34.Y. C. Lim, Y. Sun and **Y. J. Yu**, “Design of discrete-coefficient FIR filters on loosely connected parallel machines”, IEEE Trans. Signal Processing,vol. 50, pp. 1409 - 1416, June 2002.

35.**Y. J. Yu** and Y. C. Lim, “A novel genetic algorithm for the design of a signed power-of-two coefficient quadrature mirror filter lattice filter bank”, Circuit Syst. Signal Process., vol. 21, pp. 263-276, May 2002.

1.X. Lou, W. B. Ye, and **Y. J. Yu**, “Investigation on Power Consumption of Product Accumulation Block For Multiplierless FIR Filters”, in Proceedings of the 2017 International Conference on Digital Signal Processing (DSP), London, UK, Aug. 2017.

2.W. L. Chen, **Y. J. Yu** and H. J. Shi, “An Improvement of Edge-Adaptive Image Scaling Algorithm Based on Sobel Operator”, in Proceedings of the 4th International Conference on Information Science and Control Engineering (ICISCE 2017), Changsha, China, July 2017.

3.**Y. J. Yu**, Z. Yang, B.-S. Oh, Y. K. Yeo, G.-B. Huang and Z. Lin, “Investigation on Driver Stress Utilizing ECG signals with On-board Navigation Systems in Use”, in Proceedings of the 2016 International Conference on Control, Automation, Robotics and Vision (ICARCV2016), Phuket, Thailand, Nov. 2016.

4.W. B. Ye and **Y. J. Yu**, “An Efficient FIR Filtering Technique for Processing Non-uniformly Sampled Signal”, in Proceedings of the 2015 IEEE International Conference on Digital Signal Processing (DSP), Singapore, July 2015.

5.X. Lou and **Y. J. Yu**, “Area-Time Efficient Realization of Multiple Constant Multiplication”, in Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, Lisbon, Portugal, May 2015.

6.W. B. Ye, X. Lou and **Y. J. Yu**, “On the Design of High-Speed Multiplierless Linear-Phase FIR Filters”, in Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, Lisbon, Portugal, May 2015.

7.X. Lou, P. K. Meher, **Y. J. Yu**, “Fine-Grained Pipelining for Multiple Constant Multiplications”, in Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, Lisbon, Portugal, May 2015.

8.R. Fan, **Y. J. Yu** and Y. L. Guan, “Orthogonal Frequency Division Multiplexing with Generalized Index Modulation”, in Proceeding of GlobeCom 2014, Austin, TX.

9.W. B. Ye and **Y. J. Yu**, “A Polynomial-Time Algorithm for the Design of Multiplierless Linear-Phase FIR Filters with Low Hardware Cost”, in Proceedings of the 2014 IEEE International Symposium on Circuits and Systems, Melbourne, Australia, June 2014.

10.X. Lou, **Y. J. Yu** and P. K. Meher, “High-Speed Multiplier Block Design Based on Bit-Level Critical Path Optimization”, in Proceedings of the 2014 IEEE International Symposium on Circuits and Systems, Melbourne, Australia, June 2014.

11.H. Zhao, W. B. Ye and** Y. J. Yu**, “Sparse FIR Filter Design Based on Genetic Algorithm”, in Proceedings of the 2013 IEEE International Symposium on Circuits and Systems, Beijing, PRChina, May 2013.

12.W. B. Ye and **Y. J. Yu**, “Design of high order and wide coefficient wordlength multiplierless FIR filters with low hardware cost using genetic algorithm”, in Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, Seoul, South Korea, May 2012.

13.W. B. Ye and **Y. J. Yu**, “An Algorithm for the Design of Low Power Linear Phase FIR Filters”, in Proceedings of the 2011 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics, Macau, China, Oct. 2011. (Silver Leaf Certificate)

14.**Y. J. Yu**, “Design of Variable Bandedge FIR Filters with Extremely Large Bandedge Variation Range”, in Proceedings of the 2011 IEEE International Symposium on Circuits and Systems, Rio de Janeiro, Brazil, May 2011.

15.W. B. Ye and** Y. J. Yu**, “Switching Activity Analysis and Power Estimation for Multiple Constant Multiplier Block of FIR Filters”, in Proceedings of the 2011 IEEE International Symposium on Circuits and Systems, Rio de Janeiro, Brazil, May 2011.

16.D. Shi and **Y. J. Yu**, “Low-Complexity Linear Phase FIR Filters in Cascade Form”, in Proceedings of the 2010 IEEE International Symposium on Circuits and Systems, Paris, France, May 2010.

17.W. J. Xu and **Y. J. Yu**, “Polynomial Implementation Structure for Lagrange-Type Variable Fractional Delay Filters”, in Proceedings of the 2010 IEEE International Symposium on Circuits and Systems, Paris, France, May 2010.

18.P. Sun, G. Wang, W. Woods, H. Wang and **Y. J. Yu**, “An adaptive body-bias low voltage low power LC VCO”, in Proceedings of the 2010 IEEE International Symposium on Circuits and Systems, Paris, France, May 2010.

19.S. Y. Park and** Y. J. Yu**, “An Improved Structure and Design Procedure for Signed Power-of-two Lattice QMF Bank”, in Proc. 2009 International Symposium on Integrated Circuits (ISIC 2009), Singapore, Dec. 2009.

20.**Y. J. Yu** and Y. C. Lim, “Optimization of FIR Filters in Subexpression Space with Constrained Adder Depth”, in 6th International Symposium on Image and Signal Processing and Analysis (ISPA 2009), Salzburg, Austria, Sept. 2009.

21.**Y. J. Yu**, D. Shi and R. Bregovic, “On the Complexity Reduction of Polyphase Linear Phase FIR Filters with Symmetric Coefficient Implementation”, in Proceedings of the 2009 IEEE International Symposium on Circuits and Systems, Taipei, Taiwan, May 2009.

22.**Y. J. Yu**, D. Shi and Y. C. Lim, “Subexpression Encoded Extrapolated Impulse Response FIR Filter with Perfect Residual Compensation”, in Proceedings of the 2008 IEEE International Symposium on Circuits and System., Seattle, WA, May 2008.

23.**Y. J. Yu** and Y. C. Lim, "Roundoff Noise Analysis for FSK Signals in White Noise Represented as Signed Power-of-Two Numbers," in Proc. 2007 International Conference on Electronics, Circuits and Systems, Marrakech, Morocco, pp. 796-799. Dec 2007.

24.Y. C. Lim, **Y. J. Yu**, T. Saramäki and K. L. Teo, “FRM-Based FIR Filters with Minimum Coefficient Sensitivities”, in Proc. 2007 IEEE International Symposium on Circuits and Systems,

New Orleans, LA, May 2007.

25.Y. C. Lim,** Y. J. Yu**, T. Saramäki, “FRM approach for hubert transformer synthesis”, in Proc. 4th International Conference on Information Technology and Applications, ICITA 2007, Harbin, China, Jan. 2007.

26.**Y. J. Yu** and Y. C. Lim, "Roundoff Noise Analysis of Signals Represented Using Signed Power-of-Two Terms," in Proc. 14th European Signal Processing Conference EUSIPCO2006, Florence, Italy, Sept. 2006.

27.R. Bregovic, T. Saramäki, **Y. J. Yu**, Y. C. Lim, “An Efficient Implementation of Linear-Phase Fir Filters for a Rational Sampling Rate Conversion”, in Proceedings of the 2006 IEEE International Symposium on Circuits and Systems, pp. 5395-5398. Island of Kos, Greece, May 2006.

28.**Y. J. Yu**, Y. C. Lim, “Signed Power-of-Two Allocation Scheme for the Design of Lattice Orthogonal Filter Banks”, in Proceedings of the 2005 IEEE International Symposium on Circuits and Systems, pp. 1819-1822. Kobe, Japan, May 2005.

29.**Y. J. Yu**, Y. C. Lim, K. L. Teo and G. H. Zhao, "Frequency-Response Masking Technique Incorporating Extrapolated Impulse Response Band-edge Shaping Filter", in Proceedings of the 2004 IEEE International Symposium on Circuits and Systems, vol. 5. pp. 532-535. Vancouver, Canada, May 2004.

30.J. Yli-Kaakinen, T. Saramäki and **Y. J. Yu**, "An Efficient Algorithm for the Optimization of FIR Filters Synthesized Using the Multistage Frequency-Response Masking Approach", in Proceedings of the 2004 IEEE International Symposium on Circuits and Systems, vol. 5. pp. 540-543. Vancouver, Canada, May 2004.

31.**Y. J. Yu**, G. H. Zhao, K. L. Teo and Y. C. Lim, “Optimization of Extrapolated Impulse Response Filters Using Semi-Infinite Programming”, in Proceedings of 2004 First International Symposium on Control, Communications and Signal Processing, ICCSSP04, pp. 397 – 400, Hammamet, Tunisia, March 2004.

32.**Y. J. Yu**, G. H. Zhao, K. L. Teo and Y. C. Lim, "Optimization and Implementation of Extrapolated Impulse Response Filters", in Proceedings of 2003 IEEE Conf. Neural Network & Signal Processing, pp. 744-747. Nanjing, China, Dec. 2003.

33.**Y. J. Yu**,T. Saramäki and Y. C. Lim, "An iterative method for optimizing FIR filters synthesized using the two-stage frequency-response masking technique", in Proceedings of the 2003 IEEE International Symposium on Circuits and Systems,. Vol. 3. pp. 874 - 877. Bangkok, Thailand, 25-28 May 2003.

34.**Y. J. Yu** and Y. C. Lim, "Genetic algorithm approach for the optimization of multiplierless sub-filters generated by the frequency-response masking technique", in Proceedings of the 2002 IEEE International Conference on Electronics Computers and Systems, Vol. 3,pp. 1163 - 1166, Dubrovnik, Croatia, 15-18 Sept., 2002.

35.**Y. J. Yu** and Y. C. Lim, "FRM based FIR filter design - the WLS approach", in Proceedings of the 2002 IEEE International Symposium on Circuits and Systems,. Vol. 3. pp. 221 - 224. Phoenix, AZ, 26-29 May 2002.

36.**Y. J. Yu** and Y. C. Lim, "New natural selection process and chromosome encoding for the design of multiplierless lattice QMF using genetic algorithm", in Proceedings of the 2001 IEEE International Conference on Electronics Computers and Systems, Vol. 3, pp. 1273 - 1276. Malta, 2-5 Sept. 2001.

37.**Y. J. Yu** and Y. C. Lim, "A sequential reoptimization approach for the design of signed power-of-two coefficient lattice QMF bank", in Proceedings of the 2001 IEEE Region 10 International Conference on Electrical and Electronic Technology. Vol. 1, pp. 57 - 60. Singapore, 19-22 Aug. 2001.

38.Y. C. Lim, **Y. J. Yu**, H. Q. Zheng and S. W. Foo, "FPGA implementation of digital filters synthesized using the frequency-response masking technique", in Proceedings of the 2001 IEEE International Symposium on Circuits and Systems,.Vol. 2, pp. 173 - 176. Sydney, Australia, 6-9 May 2001.

39.Y. C. Lim and **Y. J. Yu**, "A successive reoptimization approach for the design of discrete coefficient perfect reconstruction lattice filter bank", in Proceedings of the 2000 IEEE International Symposium on Circuits and Systems,. Vol. 2.pp. 69 - 72.28-31, Geneva, Switzerland, May 2000.

**Digital Filter Structures and Their Implementation**

* Academic Press Library in Signal Processing: Volume 1: Signal Processing Theory and Machine Learning*, (Editor-in-Chief: Sergios Theodoridis and Rama Chellappa, Publisher: Academic Press), 2013.

1.X. Lou, P. K. Meher,** Y. J. Yu** and W. B. Ye, “Novel Structure for Area-Energy-Efficient Implementation of FIR Filter”, accepted by IEEE Transactions on Circuits and Systems II,Oct,2017.

2.W. B. Ye, X. Lou, and **Y. J. Yu**, “Design of Low Power Multiplierless Linear-Phase FIR Filters”, Accepted by IEEE Access,Aug,2017.

3.X. Lou, **Y. J. Yu** and P. K. Meher, “Lower Bound Analysis and Perturbation of Critical Path for Area-Time Efficient Multiple Constant Multiplications”, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 2, pp. 313 – 324, Feb. 2017.

4.X. Lou, **Y. J. Yu** and P. K. Meher, “Analysis and Optimization of Product-Accumulation Section for Efficient Implementation of FIR Filters”, IEEE Trans. Circuits, Syst. I, vol. 63, no. 10, pp. 1701 – 1703, Oct. 2016

5.R. Fan, **Y. J. Yu** and Y. L. Guan, “Improved Orthogonal Frequency Division Multiplexing with Generalized Index Modulation”, IET Communications, vol. 10, iss. 8, pp. 969-974, Aug. 2016.

6.W. B. Ye and **Y. J. Yu**, “Greedy Algorithm for the Design of Linear-Phase FIR Filter with Sparse Coefficients”, Circuits Systems and Signal Processing, vol. 35, no. 4, pp. 1427-1436, April 2016.

7.X. Lou, **Y. J. Yu** and P. K. Meher, “New Approach to the Reduction of Sign-extension Overhead for Efficient Implementation of Multiple Constant Multiplications”, IEEE Trans. Circuits, Syst. I., vol. 62, no. 11, pp. 2695-2705, Nov. 2015.

8.R. Fan, **Y. J. Yu** and Y. L. Guan, “Generalization of Orthogonal Frequency Division Multiplexing with Index Modulation”, IEEE Trans. Wireless Communications, vol. 14, no. 10, pp. 5350-5359, Oct. 2015.

9.W. B. Ye and **Y. J. Yu**, “Two-step Optimization Approach for the Design of Multiplierless Linear-Phase FIR Filters”, IEEE Trans. Circuits, Syst. I., vol. 62, no. 5, pp. 1279-1287, May 2015. (Invited paper for special issue of IEEE TCAS-I on best papers selected from ISCAS’14.)

10.X. Lou, **Y. J. Yu** and P. K. Meher, “Fine-Grained Critical Path Analysis and Optimization for Area-Time Efficient Realization of Multiple Constant Multiplications”, IEEE Trans. Circuits, Syst. I., vol. 62, no. 3, pp. 863-872, March 2015.

11.W. B. Ye, and **Y. J. Yu**, “Bit-level Multiplierless FIR Filter Optimization Incorporating Sparse Filter Technique”, IEEE Trans. Circuits, Syst. I., vol. 61, no. 11, pp. 3206-3215, Nov. 2014.

12.W. J. Xu, **Y. J. Yu**, and H. Johansson, “Improved Filter Bank Approach for the Design of Variable Bandedge and Fractional Delay Filters”, IEEE Trans. Circuits, Syst. I., vol. 61, no. 3, pp. 764-777, March 2014.

13.W. B. Ye, and **Y. J. Yu**, “Single Stage and Cascade Design of High Order Multiplierless linear phase FIR Filters Using Genetic Algorithm”, IEEE Trans. Circuits, Syst. I., vol. 60, no. 11, pp. 2987-2997, Nov. 2013. (Invited paper for special issue of IEEE TCAS-I on best papers selected from ISCAS’12.)

14.**Y. J. Yu**, and W. J. Xu, “Investigation on the Optimization Criteria for the Design of Variable Fractional Delay Filters”, IEEE Trans. Circuits, Syst. II., vol. 60, no. 8, pp. 522-526, Aug. 2013.

15.S. Y. Park, and **Y. J. Yu**, “Fixed-Point Analysis and Parameter Selections of MSR-CORDIC with Applications to FFT Designs”, IEEE Trans. Signal Processing, vol. 60, no. 12, pp.6245-6256, Dec. 2012.

16.**Y. J. Yu**, and W. J. Xu, “Mixed-Radix Fast Filter Bank Approach for the Design of Variable Digital Filters with Simultaneously Tunable Bandedge and Fractional Delay”, IEEE Trans. Signal Processing, vol. 60, no. 1, pp.100-111, Jan. 2012.

17.D. Shi, and **Y. J. Yu**, “Design of Discrete-valued Linear Phase FIR Filters in Cascade Form”, IEEE Trans. Circuits, Syst. I. vol. 58, no. 7, pp.1627-1636, July 2011. (Invited paper for special issue of IEEE TCAS-I on best papers selected from ISCAS’10.)

18.R. Bregovic, **Y. J. Yu**, T. Saramäki, and Y. C. Lim, “Implementation of Linear-Phase FIR Filters for a Rational Sampling Rate Conversion Utilizing the Coefficient Symmetry”, IEEE Trans. Circuits, Syst. I. vol. 58, no. 3, pp. 548-561, Mar. 2011.

19.D. Shi, and **Y. J. Yu**, “Design of Linear Phase FIR Filters with High Probability of Achieving Minimum Number of Adders”, IEEE Trans. Circuits, Syst. I. vol. 58, no. 1, pp. 126-136, Jan. 2011.

20.R. Bregovic, **Y. J. Yu**, A. Viholainen and Y. C. Lim, “Implementation of Linear-Phase FIR Nearly Perfect-Reconstruction Cosine-Modulated Filterbanks Utilizing the Coefficient Symmetry”, IEEE Trans. Circuits, Syst. I. vol. 57, no. 1, pp. 139-151, Jan. 2010.

21.Y. Lian and **Y. J. Yu**, “Guest Editorial: Low-Power Digital Filter Design Techniques and Their Applications”, Circuit Syst. Signal Process, vol. 29, no. 1, pp. 1-5, Jan. 2010.

22.**Y. J. Yu**, and Y. C. Lim, “Optimization of Linear Phase FIR Filters in Dynamically Expanding Subexpression Space”, Circuit Syst. Signal Process, vol. 29, no. 1, pp. 65-80, Feb. 2010.

23.**Y. J. Yu,** D. Shi, and Y. C. Lim, “Design of Extrapolated Impulse Response FIR Filters with Residual Compensation in Subexpression Space”, IEEE Trans. Circuits, Syst. I, vol. 56, no. 12, pp. 2621-2633, Dec. 2009.

24.**Y. J. Yu**, Y. C. Lim and D. Shi, “Low Complexity Design of Variable Bandedge Linear Phase FIR filters with Sharp Transition Band”, IEEE Trans. Signal Processing, vol. 57, no. 4, pp. 1328-1338, April 2009.

25.**Y. J. Yu** and Y. C. Lim, “Design of Linear Phase FIR Filters in Subexpression Space Using Mixed Integer Linear Programming”, IEEE Trans. Circuits, Syst. I, vol. 54, no. 10, pp. 2330-2338, Oct. 2007.

26.Y. C. Lim, **Y. J. Yu**, T. Saramäki and K. L. Teo, "FRM Based FIR Filters with Optimum Finite Word Length Performance," IEEE Trans. Signal Processing, vol. 55, pp. 2914-2924, June 2007.

27.**Y. J. Yu** and Y. C. Lim, "Roundoff Noise Analysis of Signals Represented Using Signed Power-of-Two Terms," ?IEEE Trans. Signal Processing, vol. 55, pp. 2122-2135, May 2007.

28.**Y. J. Yu**, Y. C. Lim and T. Saram?ki, “Restoring Coefficient Symmetry in Polyphase Implementation of Linear Phase FIR filters”, Circuit Syst. Signal Process., vol. 25, pp. 253-264, Apr 2006.

29.Y. C. Lim, **Y. J. Yu** and T. Saram?ki, “Optimum masking levels and coefficient sparseness for Hilbert transformers and half-band filters designed using the frequency-response masking technique,” IEEE Trans. Circuits, Syst. I, vol 52, no. 11, pp. 2444-2453, Nov 2005.

30.Y. C. Lim and **Y. J. Yu**, “Synthesis of Very Sharp Hilbert Transformer Using the Frequency-Response Masking Technique,” IEEE Trans. Signal Process., vol. 53, no. 7, pp. 2595-2597, July 2005.

31.**Y. J. Yu**, K. L. Teo, Y. C. Lim, and G. H. Zhao., “Extrapolated Impulse Response Filter and its Application in the Synthesis of Digital Filters Using the Frequency-Response Masking Technique,” Signal Processing (Elsevier), Vol 85/3 pp. 581-590, March 2005.

32.Y. C. Lim and **Y. J. Yu**, “A width-recursive depth-first tree search approach for the design of discrete coefficient perfect reconstruction lattice filter bank,” IEEE Trans. Circuits, Syst. II, vol. 50, pp. 257-266, June 2003.

33.Y. C. Lim, **Y. J. Yu**, H. Q. Zheng and S. W. Foo, “FPGA implementation of digital filters synthesized using the FRM technique,” Circuit Syst. Signal Process., vol. 22, pp. 211-218, March 2003.

34.Y. C. Lim, Y. Sun and **Y. J. Yu**, “Design of discrete-coefficient FIR filters on loosely connected parallel machines”, IEEE Trans. Signal Processing,vol. 50, pp. 1409 - 1416, June 2002.

35.**Y. J. Yu** and Y. C. Lim, “A novel genetic algorithm for the design of a signed power-of-two coefficient quadrature mirror filter lattice filter bank”, Circuit Syst. Signal Process., vol. 21, pp. 263-276, May 2002.

1.X. Lou, W. B. Ye, and **Y. J. Yu**, “Investigation on Power Consumption of Product Accumulation Block For Multiplierless FIR Filters”, in Proceedings of the 2017 International Conference on Digital Signal Processing (DSP), London, UK, Aug. 2017.

2.W. L. Chen, **Y. J. Yu** and H. J. Shi, “An Improvement of Edge-Adaptive Image Scaling Algorithm Based on Sobel Operator”, in Proceedings of the 4th International Conference on Information Science and Control Engineering (ICISCE 2017), Changsha, China, July 2017.

3.**Y. J. Yu**, Z. Yang, B.-S. Oh, Y. K. Yeo, G.-B. Huang and Z. Lin, “Investigation on Driver Stress Utilizing ECG signals with On-board Navigation Systems in Use”, in Proceedings of the 2016 International Conference on Control, Automation, Robotics and Vision (ICARCV2016), Phuket, Thailand, Nov. 2016.

4.W. B. Ye and **Y. J. Yu**, “An Efficient FIR Filtering Technique for Processing Non-uniformly Sampled Signal”, in Proceedings of the 2015 IEEE International Conference on Digital Signal Processing (DSP), Singapore, July 2015.

5.X. Lou and **Y. J. Yu**, “Area-Time Efficient Realization of Multiple Constant Multiplication”, in Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, Lisbon, Portugal, May 2015.

6.W. B. Ye, X. Lou and **Y. J. Yu**, “On the Design of High-Speed Multiplierless Linear-Phase FIR Filters”, in Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, Lisbon, Portugal, May 2015.

7.X. Lou, P. K. Meher, **Y. J. Yu**, “Fine-Grained Pipelining for Multiple Constant Multiplications”, in Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, Lisbon, Portugal, May 2015.

8.R. Fan, **Y. J. Yu** and Y. L. Guan, “Orthogonal Frequency Division Multiplexing with Generalized Index Modulation”, in Proceeding of GlobeCom 2014, Austin, TX.

9.W. B. Ye and **Y. J. Yu**, “A Polynomial-Time Algorithm for the Design of Multiplierless Linear-Phase FIR Filters with Low Hardware Cost”, in Proceedings of the 2014 IEEE International Symposium on Circuits and Systems, Melbourne, Australia, June 2014.

10.X. Lou, **Y. J. Yu** and P. K. Meher, “High-Speed Multiplier Block Design Based on Bit-Level Critical Path Optimization”, in Proceedings of the 2014 IEEE International Symposium on Circuits and Systems, Melbourne, Australia, June 2014.

11.H. Zhao, W. B. Ye and** Y. J. Yu**, “Sparse FIR Filter Design Based on Genetic Algorithm”, in Proceedings of the 2013 IEEE International Symposium on Circuits and Systems, Beijing, PRChina, May 2013.

12.W. B. Ye and **Y. J. Yu**, “Design of high order and wide coefficient wordlength multiplierless FIR filters with low hardware cost using genetic algorithm”, in Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, Seoul, South Korea, May 2012.

13.W. B. Ye and **Y. J. Yu**, “An Algorithm for the Design of Low Power Linear Phase FIR Filters”, in Proceedings of the 2011 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics, Macau, China, Oct. 2011. (Silver Leaf Certificate)

14.**Y. J. Yu**, “Design of Variable Bandedge FIR Filters with Extremely Large Bandedge Variation Range”, in Proceedings of the 2011 IEEE International Symposium on Circuits and Systems, Rio de Janeiro, Brazil, May 2011.

15.W. B. Ye and** Y. J. Yu**, “Switching Activity Analysis and Power Estimation for Multiple Constant Multiplier Block of FIR Filters”, in Proceedings of the 2011 IEEE International Symposium on Circuits and Systems, Rio de Janeiro, Brazil, May 2011.

16.D. Shi and **Y. J. Yu**, “Low-Complexity Linear Phase FIR Filters in Cascade Form”, in Proceedings of the 2010 IEEE International Symposium on Circuits and Systems, Paris, France, May 2010.

17.W. J. Xu and **Y. J. Yu**, “Polynomial Implementation Structure for Lagrange-Type Variable Fractional Delay Filters”, in Proceedings of the 2010 IEEE International Symposium on Circuits and Systems, Paris, France, May 2010.

18.P. Sun, G. Wang, W. Woods, H. Wang and **Y. J. Yu**, “An adaptive body-bias low voltage low power LC VCO”, in Proceedings of the 2010 IEEE International Symposium on Circuits and Systems, Paris, France, May 2010.

19.S. Y. Park and** Y. J. Yu**, “An Improved Structure and Design Procedure for Signed Power-of-two Lattice QMF Bank”, in Proc. 2009 International Symposium on Integrated Circuits (ISIC 2009), Singapore, Dec. 2009.

20.**Y. J. Yu** and Y. C. Lim, “Optimization of FIR Filters in Subexpression Space with Constrained Adder Depth”, in 6th International Symposium on Image and Signal Processing and Analysis (ISPA 2009), Salzburg, Austria, Sept. 2009.

21.**Y. J. Yu**, D. Shi and R. Bregovic, “On the Complexity Reduction of Polyphase Linear Phase FIR Filters with Symmetric Coefficient Implementation”, in Proceedings of the 2009 IEEE International Symposium on Circuits and Systems, Taipei, Taiwan, May 2009.

22.**Y. J. Yu**, D. Shi and Y. C. Lim, “Subexpression Encoded Extrapolated Impulse Response FIR Filter with Perfect Residual Compensation”, in Proceedings of the 2008 IEEE International Symposium on Circuits and System., Seattle, WA, May 2008.

23.**Y. J. Yu** and Y. C. Lim, "Roundoff Noise Analysis for FSK Signals in White Noise Represented as Signed Power-of-Two Numbers," in Proc. 2007 International Conference on Electronics, Circuits and Systems, Marrakech, Morocco, pp. 796-799. Dec 2007.

24.Y. C. Lim, **Y. J. Yu**, T. Saramäki and K. L. Teo, “FRM-Based FIR Filters with Minimum Coefficient Sensitivities”, in Proc. 2007 IEEE International Symposium on Circuits and Systems,

New Orleans, LA, May 2007.

25.Y. C. Lim,** Y. J. Yu**, T. Saramäki, “FRM approach for hubert transformer synthesis”, in Proc. 4th International Conference on Information Technology and Applications, ICITA 2007, Harbin, China, Jan. 2007.

26.**Y. J. Yu** and Y. C. Lim, "Roundoff Noise Analysis of Signals Represented Using Signed Power-of-Two Terms," in Proc. 14th European Signal Processing Conference EUSIPCO2006, Florence, Italy, Sept. 2006.

27.R. Bregovic, T. Saramäki, **Y. J. Yu**, Y. C. Lim, “An Efficient Implementation of Linear-Phase Fir Filters for a Rational Sampling Rate Conversion”, in Proceedings of the 2006 IEEE International Symposium on Circuits and Systems, pp. 5395-5398. Island of Kos, Greece, May 2006.

28.**Y. J. Yu**, Y. C. Lim, “Signed Power-of-Two Allocation Scheme for the Design of Lattice Orthogonal Filter Banks”, in Proceedings of the 2005 IEEE International Symposium on Circuits and Systems, pp. 1819-1822. Kobe, Japan, May 2005.

29.**Y. J. Yu**, Y. C. Lim, K. L. Teo and G. H. Zhao, "Frequency-Response Masking Technique Incorporating Extrapolated Impulse Response Band-edge Shaping Filter", in Proceedings of the 2004 IEEE International Symposium on Circuits and Systems, vol. 5. pp. 532-535. Vancouver, Canada, May 2004.

30.J. Yli-Kaakinen, T. Saramäki and **Y. J. Yu**, "An Efficient Algorithm for the Optimization of FIR Filters Synthesized Using the Multistage Frequency-Response Masking Approach", in Proceedings of the 2004 IEEE International Symposium on Circuits and Systems, vol. 5. pp. 540-543. Vancouver, Canada, May 2004.

31.**Y. J. Yu**, G. H. Zhao, K. L. Teo and Y. C. Lim, “Optimization of Extrapolated Impulse Response Filters Using Semi-Infinite Programming”, in Proceedings of 2004 First International Symposium on Control, Communications and Signal Processing, ICCSSP04, pp. 397 – 400, Hammamet, Tunisia, March 2004.

32.**Y. J. Yu**, G. H. Zhao, K. L. Teo and Y. C. Lim, "Optimization and Implementation of Extrapolated Impulse Response Filters", in Proceedings of 2003 IEEE Conf. Neural Network & Signal Processing, pp. 744-747. Nanjing, China, Dec. 2003.

33.**Y. J. Yu**,T. Saramäki and Y. C. Lim, "An iterative method for optimizing FIR filters synthesized using the two-stage frequency-response masking technique", in Proceedings of the 2003 IEEE International Symposium on Circuits and Systems,. Vol. 3. pp. 874 - 877. Bangkok, Thailand, 25-28 May 2003.

34.**Y. J. Yu** and Y. C. Lim, "Genetic algorithm approach for the optimization of multiplierless sub-filters generated by the frequency-response masking technique", in Proceedings of the 2002 IEEE International Conference on Electronics Computers and Systems, Vol. 3,pp. 1163 - 1166, Dubrovnik, Croatia, 15-18 Sept., 2002.

35.**Y. J. Yu** and Y. C. Lim, "FRM based FIR filter design - the WLS approach", in Proceedings of the 2002 IEEE International Symposium on Circuits and Systems,. Vol. 3. pp. 221 - 224. Phoenix, AZ, 26-29 May 2002.

36.**Y. J. Yu** and Y. C. Lim, "New natural selection process and chromosome encoding for the design of multiplierless lattice QMF using genetic algorithm", in Proceedings of the 2001 IEEE International Conference on Electronics Computers and Systems, Vol. 3, pp. 1273 - 1276. Malta, 2-5 Sept. 2001.

37.**Y. J. Yu** and Y. C. Lim, "A sequential reoptimization approach for the design of signed power-of-two coefficient lattice QMF bank", in Proceedings of the 2001 IEEE Region 10 International Conference on Electrical and Electronic Technology. Vol. 1, pp. 57 - 60. Singapore, 19-22 Aug. 2001.

38.Y. C. Lim, **Y. J. Yu**, H. Q. Zheng and S. W. Foo, "FPGA implementation of digital filters synthesized using the frequency-response masking technique", in Proceedings of the 2001 IEEE International Symposium on Circuits and Systems,.Vol. 2, pp. 173 - 176. Sydney, Australia, 6-9 May 2001.

39.Y. C. Lim and **Y. J. Yu**, "A successive reoptimization approach for the design of discrete coefficient perfect reconstruction lattice filter bank", in Proceedings of the 2000 IEEE International Symposium on Circuits and Systems,. Vol. 2.pp. 69 - 72.28-31, Geneva, Switzerland, May 2000.

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