VLSI Digital filter design:
Design and implementation of low-power, high-performance and high-speed FIR filter/filter bank and variable filters, sampling rate converters. The researches are conducted at algorithm level, structure level, and circuit level.
Digital Signal processing:
Signal statistics analysis, finite wordlength analysis, distributed signal processing, signal processing on graph.
Signal processing for communication:
Filter-bank multi-carrier communication, modulation for communication Research Activities.
2011: Silver Leaf Certificate received by Ph.D student, Ye Wenbin, at 2011 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia 2011) for the paper “An algorithm for the design of low power linear phase FIR filters”. The Silver Leaf Certificate recognizes the top 20% papers presented in the conference.
2009: IEEE Circuits and Systems Singapore Chapter Graduate Student Award with a cash prize of S$200 received by Ph.D student Shi Dong.
1997: Recipient of the 1997 Scientific and Technological Progress Award of Zhejiang Province, PRC - Bronze. The award is to recognize the highest scientific and technological achievements in relevant areas in Zhejiang Province during the calendar year preceding the award. The award is based on the general quality, promotion to the scientific and technological progress, and social and economic impacts.
(a)Project co-principal investigator for“Study on the Evaluation of Vehicle Navigation System Pressure on Drivers Based on Very Short Term Heart Rate Variation Index”，01/2018 –12/2020，funded by Shenzhen kechuang free inquiry (RMB300,000).
(b) Project co-principal investigator for“Exploring the "task based" teaching mode of "digital system design" course ”，01/2018 –12/2019，funded by Shenzhen Municipal Science and Technology Innovation Committee(RMB80,000).
(c) Project co-principal investigator for “Filter Bank Multicarrier Communications” of Advanced Communication Research Project Phase III, 09/2014 – 11/2016, DSO/DSTA (S$400,000).
(d) Project principal investigator for “Sampling Rate Converter (SRC) & Its FPGA Implementation”, 01/2011 – 04/2013, funded by Ministry of Defense (S$403,000).
(e) Project principal investigator for “Circuit and System Design for Digital Signal Processing”, 04/2006 –12/2015, Temasek Lab@NTU Seed Project (S$72,000).
(f) Project PI for “Investigation, Design and Optimization of Non-uniformly Sampled Signal Processing System”, 03/2014 – 02/2016, AcRF Tier 1, (S$98,800).
(g) Project PI for “VLSI Digital Filter Design and Implementation”, 12/2006-11/2008, SUG of COE,(S$70,000)
2015 – 2016：Deputy Chair, IEEE CAS Singapore Chapter Committee
2014 – ：Treasurer, IEEE CAS Singapore Chapter Committee.
2013 – ：Secretary, IEEE CAS Singapore Chapter Committee.
2012 – :Deputy Chair, IEEE CAS Singapore Chapter Committee.
2010 – 2011：Treasurer, IEEE CAS Singapore Chapter Committee.
2008 – 2009：Deputy Chair, IEEE CAS Singapore Chapter Committee.
2007 – ：Member, IEEE Circuits and Systems Society, DSP Technical Committee.
2007 – 2008：Secretary, IEEE APCCAS steering committee.
2006 – 2007：Treasurer, IEEE CAS Singapore Chapter Committee.
2016 – ：IEEE Trans. on Circuits and System I.
2009 – 2017：Circuit Systems and Signal Processing.
2010 – 2013：IEEE Trans. on Circuits and Systems II.
Editorial Board Member (equivalent to Associate Editor):
2015 – 2017：Digital Signal Processing, Elsevier.
2007 – 2009：Circuits Systems and Signal Processing, special issue on “Low Power Digital Filter Design Techniques and Their Applications”, Jan. 2010.
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