Assistant Professor School of Microelectronics

Dr. Pan quan, Bachelor's degree in electronic science and technology, university of science and technology of China; doctor's degree in electronic and computer engineering, Hong Kong university of science and technology. From 2005 to 2009, he worked as an rf chip engineer in Beijing times minxin technology co. LTD. From 2014 to 2018, he worked as a senior executive engineer at eTopus Technology Inc. a silicon valley high-speed hardware startup. Prof. PAN Quan’s main research interests are high-speed analog/RF IC designs, which include Wireline/Wireless high-speed communication ICs (both receiver and transmitter), Serdes/clock and recovery (CDR) circuits, LNA/frequency synthesizer, GaN IC, Si-Photonics. He has published multiple high-quality journals/conference papers, and he has more than 8-year industry experience, including 4-year state-of-the-art industry experience in Silicon Valley IC startup. In 2014, he won the innovation award of the 4th HKUST million dollar entrepreneurship competition, and in 2017, he was awarded the outstanding young author award by IEEE circuit systems association.

Personal Profile

Dr. Quan pan's research work focuses on high-speed analog/rf integrated circuit design, including Wireline/Wireless high-speed communication integrated circuit (receiver/transmitter), Serdes/clock and data recovery (CDR) circuit, low noise amplifier/frequency synthesizer, GaN integrated circuit and silicon optical interconnection research.As the project leader, I not only published many high-level academic papers in international mainstream conferences/journals, but also had more than 8 years of rich domestic and foreign work experience, including 4 years of cutting-edge work experience in silicon valley industry.

Industrial projects I have participated in include:

(1) design of eight-channel 400G pam-4 transceiver chip for data center, process: TSMC series of 28nm/16nm/12nm/7nm, complete the transformation of IP achievements

(2) research and development of 28GHz low-noise ring phase-locked ring, process: TSMC 28nm/16nm series, complete the transformation of IP results

(3) research and development of GPS/ Beidou /GNSS satellite navigation receiver front-end chip, technology: Jazz 0.35 m, completed the development of prototype chip




Optical communication integrated circuit, Wireline/Serdes/TIA/CDR circuit

Analog/rf integrated circuit, 5G/ MMW integrated circuit design (CMOS, GaN, etc.)

Chip level and board level EMI and noise analysis, high-performance layout optimization analysis

Biomedical chip and sensor chip

Research on silicon optical interconnection


Main courses: Analog integrated circuit design (for undergraduate),Rf communication integrated circuit and system design (for postgraduate)

Attending courses: not available

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The research results are mainly published in IEEE and other academic journals, representing the following articles:

1. J. Hu, Z. Zhang, Q. Huang, J. Yang, M. Hu, Q. Jiang Y. Guo, Q.Pan “An 18-Gb/s 36×13-µm2 3.53-mW 2^7-1 PRBS Generator in 40-nm CMOS”2020 IEEE International Conference on Electronics, Information, and Communication (ICEIC), Barcelona, Spain, Jan. 2020

2. M. Tang, Z. Li, J. Hu, Q. Huang, N, Qi, H.Yu, Q. Pan, "A 56-Gb/s PAM4 Continuous-Time Linear Equalizer with Fixed Peaking Frequency in 40-nm CMOS," 2019 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA), Cheng'du, China, Nov. 2019.

3. Z. Li, M. Tang, Y. Guo, Q. Huang and Q. Pan, "A 56-Gb/s PAM4 Variable Gain Amplifier in 40-nm CMOS Technology," in 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Xi'an, China, 2019, pp. 1―3.

4. J. Wang, Q. Pan* et al., "A Fully-Integrated 25Gb/s Low-Noise TIA+CDR Optical Receiver Designed in 40nm-CMOS," TCAS-II, DOI 10.1109/TCSII.2019.2925363, Jun. 2019.

5. Q. Pan et al., “A 42-dBΩ 25-Gb/s CMOS Transimpedance Amplifier with Multiple-Peaking Scheme for Optical Communications,” IEEE Transactions on Circuits and Systems II: Express Briefs, Feb. 2019.

6. Y. Guo, and Q. Pan, “A PAM-4 80-Gb/S Variable-Gain Transimpedance Amplifier in 40-nm CMOS Technology,” in IEEE International Conference on Integrated Circuits, Technologies and Applications, Nov. 2018.

7. Q. Pan, Y. Wang, Z. Hou, L. Sun, L. Wu, W. H. Ki, P. Chiang, and C. P. Yue, “A 41-mW 30-Gb/s CMOS Optical Receiver with Digitally-Tunable Cascaded Equalization,” in Proc. European Solid-State Circuits Conf., Sep. 2014.

8. Q. Pan, Z. Hou, Y. Wang, Y. Lu, W. H. Ki, K. C. Wang, and C. P. Yue, “A 48-mW 18-Gb/s Fully Integrated CMOS Optical Receiver with Photodetector and Adaptive Equalizer,” in Symp. VLSI Circuits Dig. Tech. Papers, pp. 116−117, Jun. 2014.

9. Q. Pan, Z. Hou, Y. Li, A. W. Poon, and C. P. Yue, “A 0.5-V P-Well/Deep N-Well photodetector in 65-nm CMOS for monolithic 850-nm optical receivers,” IEEE Photonics Technology Letters (PTL), vol. 26, no. 12, pp. 1184−1187, Jun. 2014.

10. Q. Pan, T. J. Yeh, C. Jou, F. L. Hsueh, H. Luong, and C. P. Yue, “A performance study of layout and Vt options for low noise amplifier design in 65-nm CMOS,” in IEEE Radio Frequency Integrated Circuits Symp., pp. 535−538, Jun. 2012.

11. G. Zhu, Q. Pan, J. Zhuang, C. Zhi, and C. P. Yue, “A Low-Power PAM4 Receiver Using 1/4-Rate Sampling Decoder with Adaptive Variable-Gain Rectification,” in 2017 IEEE Asian Solid-State Circuits Conf., Nov. 2017.

12. Y. Wang, D. Luo, Q. Pan, L. Jing, Z. Li, and C. P. Yue, “A 60-GHz 4-Gb/s Fully Integrated NRZ-to-QPSK Fiber-Wireless Modulator,” IEEE Transactions of Circuits and Systems−I (TCAS-I), vol. 64, issue. 3, pp. 653−663, Mar. 2017.

13. L. Sun, Q. Pan, K. C. Wang, and C. P. Yue, “A 26-28-Gb/s clock and data recovery circuit with embedded equalizer in 65-nm CMOS,” IEEE Transactions of Circuits and Systems−I (TCAS-I), vol. 61, no. 7, pp. 2139−2149, Jul. 2014.

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