Assistant Professor School of Microelectronics
Dr. Pan quan, Bachelor's degree in electronic science and technology, university of science and technology of China; doctor's degree in electronic and computer engineering, Hong Kong university of science and technology. From 2005 to 2009, he worked as an rf chip engineer in Beijing times minxin technology co. LTD. From 2014 to 2018, he worked as a senior executive engineer at eTopus Technology Inc. a silicon valley high-speed hardware startup. Prof. PAN Quan’s main research interests are high-speed analog/RF IC designs, which include Wireline/Wireless high-speed communication ICs (both receiver and transmitter), Serdes/clock and recovery (CDR) circuits, LNA/frequency synthesizer, GaN IC, Si-Photonics. He has published multiple high-quality journals/conference papers, and he has more than 8-year industry experience, including 4-year state-of-the-art industry experience in Silicon Valley IC startup. In 2014, he won the innovation award of the 4th HKUST million dollar entrepreneurship competition, and in 2017, he was awarded the outstanding young author award by IEEE circuit systems association.
Dr. Quan pan's research work focuses on high-speed analog/rf integrated circuit design, including Wireline/Wireless high-speed communication integrated circuit (receiver/transmitter), Serdes/clock and data recovery (CDR) circuit, low noise amplifier/frequency synthesizer, GaN integrated circuit and silicon optical interconnection research.As the project leader, I not only published many high-level academic papers in international mainstream conferences/journals, but also had more than 8 years of rich domestic and foreign work experience, including 4 years of cutting-edge work experience in silicon valley industry.
Industrial projects I have participated in include:
(1) design of eight-channel 400G pam-4 transceiver chip for data center, process: TSMC series of 28nm/16nm/12nm/7nm, complete the transformation of IP achievements
(2) research and development of 28GHz low-noise ring phase-locked ring, process: TSMC 28nm/16nm series, complete the transformation of IP results
(3) research and development of GPS/ Beidou /GNSS satellite navigation receiver front-end chip, technology: Jazz 0.35 m, completed the development of prototype chip
Optical communication integrated circuit, Wireline/Serdes/TIA/CDR circuit
Analog/rf integrated circuit, 5G/ MMW integrated circuit design (CMOS, GaN, etc.)
Chip level and board level EMI and noise analysis, high-performance layout optimization analysis
Biomedical chip and sensor chip
Research on silicon optical interconnection
Main courses: Analog integrated circuit design (for undergraduate)，Rf communication integrated circuit and system design (for postgraduate)
Attending courses: not available
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