Assistant Professor School of Microelectronics

Dr. Pan quan, Bachelor's degree in electronic science and technology, university of science and technology of China; doctor's degree in electronic and computer engineering, Hong Kong university of science and technology. From 2005 to 2009, he worked as an rf chip engineer in Beijing times minxin technology co. LTD. From 2014 to 2018, he worked as a senior executive engineer at eTopus Technology Inc. a silicon valley high-speed hardware startup. Prof. PAN Quan’s main research interests are high-speed analog/RF IC designs, which include Wireline/Wireless high-speed communication ICs (both receiver and transmitter), Serdes/clock and recovery (CDR) circuits, LNA/frequency synthesizer, GaN IC, Si-Photonics. He has published multiple high-quality journals/conference papers, and he has more than 8-year industry experience, including 4-year state-of-the-art industry experience in Silicon Valley IC startup. In 2014, he won the innovation award of the 4th HKUST million dollar entrepreneurship competition, and in 2017, he was awarded the outstanding young author award by IEEE circuit systems association.

Personal Profile

Prof. PAN Quan’s main research interests are high-speed analog/RF IC designs, which include Wireline/Wireless high-speed communication ICs (both receiver and transmitter), Serdes/clock and recovery (CDR) circuits, LNA/frequency synthesizer, GaN IC, Si-Photonics. He has published multiple high-quality journals/conference papers, and he has more than 8-year industry experience, including 4-year state-of-the-art industry experience in Silicon Valley IC startup.

Working Experience

2018-Present ------ Assistant Professor, Southern University of Science and Technology

2014-2018------ Senior Staff Engineer, eTopus Technology Inc. (Silicon Valley VC-backed high-speed IC Startup)

2005-2009     ------RFIC Engineer, Beijing MXTronicx

Education Background

2014D.  Department of Electrical and Computer Engineering, the Hong Kong University of Science and Technology

2005S.    Department of Electrical Engineering, University of Science and Technology of China

Major Recognition

Outstanding Young Author Award, IEEE Circuits and Systems Society, 2017.

Innovation Prize Winner, the 4th Annual HKUST One Million Dollar Entrepreneurship Competition, 2014.

Research Areas

Optical communication integrated circuits

Silicon Photonic Interconnects

Serdes/CDR

Analog/RF integrated circuits

GaN integrated circuits

Research

Optical communication integrated circuit, Wireline/Serdes/TIA/CDR circuit

Analog/rf integrated circuit, 5G/ MMW integrated circuit design (CMOS, GaN, etc.)

Chip level and board level EMI and noise analysis, high-performance layout optimization analysis

Biomedical chip and sensor chip

Research on silicon optical interconnection


Teaching

Main courses: Analog integrated circuit design (for undergraduate),Rf communication integrated circuit and system design (for postgraduate)

Attending courses: not available


Publications Read More

The research results are mainly published in IEEE and other academic journals, representing the following articles:

[J04] Q. Pan, Y. Wang, and C. P. Yue, “A 42-dBΩ 25-Gb/s CMOS Transimpedance Amplifier with Multiple-Peaking Scheme for Optical Communications,” IEEE Transactions of Circuits and Systems−II (TCAS-II), accepted, 2019.

[J03] Q. Pan, Y. Wang, Y. Lu, and C. P. Yue, “An 18-Gb/s Fully Integrated Optical Receiver with Adaptive Cascaded Equalizer,” IEEE Journal of Selected Topics in Quantum Electronics, vol. 22, no. 6, Nov./Dec. 2016.

[J02] Q. Pan, Y. Wang, Z. Hou, L. Sun, Y. Lu, L. Wu, W. H. Ki, P. Chiang, and C. P. Yue, “A 30-Gb/s 1.37-pJ/b CMOS Receiver for Optical Interconnects,” IEEE Journal of Lightwave Technology, vol. 33, no. 4, pp. 778−786, Feb. 2015.

[J01] Q. Pan, Z. Hou, Y. Li, A. W. Poon, and C. P. Yue, “A 0.5-V P-Well/Deep N-Well photodetector in 65-nm CMOS for monolithic 850-nm optical receivers,” IEEE Photonics Technology Letters, vol. 26, no. 12, pp. 1184−1187, Jun. 2014.

[C03] Q. Pan, Y. Wang, Z. Hou, L. Sun, L. Wu, W. H. Ki, P. Chiang, and C. P. Yue, “A 41-mW 30-Gb/s CMOS Optical Receiver with Digitally-Tunable Cascaded Equalization,” in Proc. European Solid-State Circuits Conf., Sep. 2014.

[C02] Q. Pan, Z. Hou, Y. Wang, Y. Lu, W. H. Ki, K. C. Wang, and C. P. Yue, “A 48-mW 18-Gb/s Fully Integrated CMOS Optical Receiver with Photodetector and Adaptive Equalizer,” in Symp. VLSI Circuits Dig. Tech. Papers, pp. 116−117, Jun. 2014.

[C01] Q. Pan, T. J. Yeh, C. Jou, F. L. Hsueh, H. Luong, and C. P. Yue, “A performance study of layout and Vt options for low noise amplifier design in 65-nm CMOS,” in IEEE Radio Frequency Integrated Circuits Symp., pp. 535−538, Jun. 2012.

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