Publications

  • Journal Papers

Journal Papers

[J10]Q.Pan,L.Wang, X.Luo, and C. P.Yue"A Low-Power PAM4 Receiver with an Adaptive Variable-Gain Rectifier Based Decoder ,"TVLSI, 2020.

[J09]J.Hu, Z.Zhang ,Q.Pan,"A 15-Gb/s 0.0037-mm2 0.019-pJ/Bit Full-Rate Programmable Multi-Pattern Pseudo-Random Binary Sequence Generator ,"IEEE Transactions On Circuits And Systems II: Express Briefs, 2020.

[J08]Q.Pan,Y.Wang,and C. P.Yue,"A 42-dB \Omega~25 -Gb/s CMOS
Transimpedance Amplifier with Multiple-Peaking Scheme for Optical Communications,"IEEE
Transactions On Circuits And Systems II: Express Briefs,issue. 67(1),pp. 72−76, 2020.

[J07] J. Wang, Q. Pan* et al., "A Fully-Integrated 25Gb/s Low-Noise TIA+CDR Optical Receiver Designed in 40nm-CMOS," TCAS-II, DOI 10.1109/TCSII.2019.2925363, Jun. 2019., “A 42-dBΩ 25-Gb/s CMOS Transimpedance Amplifier with Multiple-Peaking Scheme for Optical Communications,” IEEE Transactions on Circuits and Systems II: Express Briefs, Feb. 2019.

[J06] Y. Wang, D. Luo, Q. Pan, L. Jing, Z. Li, and C. P. Yue, “A 60-GHz 4-Gb/s Fully Integrated NRZ-to-QPSK Fiber-Wireless Modulator,” IEEE Transactions of Circuits and Systems−I (TCAS-I), vol. 64, issue. 3, pp. 653−663, Mar. 2017.

[J05] Q. Pan, Y. Wang, Y. Lu, and C. P. Yue, “An 18-Gb/s Fully Integrated Optical Receiver with Adaptive Cascaded Equalizer,” IEEE Journal of Selected Topics in Quantum Electronics (JSTQE), vol. 22, no. 6, Nov./Dec. 2016. (Top-level optical/electrical journal. CMOS optical receiver research including both

optical device and electrical circuits)

[J04] Y. Lu, Y. Wang, Q. Pan, C. P. Yue, and W. H. Ki, “A Fully-Integrated Low-Dropout Regulator with Ultra-Fast Transient Response and Full-Spectrum Power Supply Rejection,”IEEE Transactions of Circuits and Systems−I (TCAS-I), vol. 63, no. 3, pp. 707−716, Mar. 2015.

[J03] Q. Pan, Y. Wang, Z. Hou, L. Sun, Y. Lu, L. Wu, W. H. Ki, P. Chiang, and C. P. Yue, “A 30-Gb/s 1.37-pJ/b CMOS Receiver for Optical Interconnects,”IEEE Journal of Lightwave Technology (JLT), vol. 33, no. 4, pp. 778−786, Feb. 2015. (Top-level optical journal. High-speed CMOS optical circuits research)

On/Before 2014:

[J02] L. Sun, Q. Pan, K. C. Wang, and C. P. Yue, “A 26-28-Gb/s clock and data recovery circuit with embedded equalizer in 65-nm CMOS,” IEEE Transactions of Circuits and Systems−I (TCAS-I), vol. 61, no. 7, pp. 2139−2149, Jul. 2014.

[J01] Q. Pan, Z. Hou, Y. Li, A. W. Poon, and C. P. Yue, “A 0.5-V P-Well/Deep N-Well photodetector in 65-nm CMOS for monolithic 850-nm optical receivers,”IEEE Photonics Technology Letters (PTL), vol. 26, no. 12, pp. 1184−1187, Jun. 2014. (Top-level optical journal. Optical device research)

Conference Papers

[C20Xin Wang , Yi Peng , Yuanxi Zhang , Tao Xia , Yifan Wu , Juncheng Wang , Lei Wang , Liujia Song ,Lei Zhao ,Shenglong Zhuo , Quan Pan ,Xuefeng Chen , Patrick Yin Chiang and  Rui Bai  “A 25Gb/s-PAM4 Optical Transceiver Chipset for 5G Optical Front-Haul ”2020 Optical Fiber Communications Conference and Exhibition (OFC).2020

[C19J. Hu, Z. Zhang, Q. Huang, J. Yang, M. Hu, Q. Jiang Y. Guo, Q.Pan “An 18-Gb/s 36×13-µm2 3.53-mW 2^7-1 PRBS Generator in 40-nm CMOS”2020 IEEE International Conference on Electronics, Information, and Communication (ICEIC), Barcelona, Spain, Jan. 2020

[C18M. Tang, Z. Li, J. Hu, Q. Huang, N, Qi, H.Yu, Q. Pan, "A 56-Gb/s PAM4 Continuous-Time Linear Equalizer with Fixedin Peaking Frequency in 40-nm CMOS," 2019 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA), Cheng'du, China, Nov. 2019.

[C17] S. Hu, T. Yao, T. Yao, B. Yin, C. Song, L. Zhao, J. Wang, R. Bai, X. Wang, T. Xia, Y. Peng, B. Yao, Y. Li, Q. Pan, Nan Qi, X. Chen, P. Y. Chiang, “A 50Gb/s PAM-4 Retimer-embedded VCSEL Driver with Asymmetric Pulsed Pre-emphasis in 40nm CMOS”, Optical Fiber Communication Conference and Exhibit. Technical Digest (OFC), Mar. 2019.

[C16Z. Li, M. Tang, Y. Guo, Q. Huang and Q. Pan, "A 56-Gb/s PAM4 Variable Gain Amplifier in 40-nm CMOS Technology," in 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Xi'an, China, 2019, pp. 1―3.

[C15] Y. Guo and Q. Pan, “A PAM-4 80-Gb/S Variable-Gain Transimpedance Amplifier in 40-nm CMOS Technology,”in IEEE International Conference on Integrated Circuits,Technologies and Applications, Nov. 2018.

[C14] G. Zhu, Q. Pan, J. Zhuang, C. Zhi, and C. P. Yue, “A Low-Power PAM4 Receiver Using 1/4-Rate Sampling Decoder with Adaptive Variable-Gain Rectification,” in 2017 IEEE Asian Solid-State Circuits Conf., Nov. 2017.

[C13] Y. Wang, D. Luo, Q. Pan, L. Jing, Z. Li, and C. P. Yue, “A 60GHz 4Gb/s Fully Integrated NRZ-to-QPSK Modulator SoC for Backhaul Links in Fiber-Wireless Networks,”in Proc. European Solid-State Circuits Conf., Sep. 2015.

On/Before 2014:

[C12] Q. Pan, Y. Wang, Z. Hou, L. Sun, L. Wu, W. H. Ki, P. Chiang, and C. P. Yue, “A 41-mW 30-Gb/s CMOS Optical Receiver with Digitally-Tunable Cascaded Equalization,”in Proc. European Solid-State Circuits Conf., Sep. 2014. (Top-level circuits conference. High-speed CMOS optical circuits)

[C11] Q. Pan, L. Sun, and C. P. Yue, “Differential Stacked Spiral Inductor and Transistor Layout Designs for Broadband High-Speed Circuits,”in IEEE Radio Frequency Integration Technology, Aug. 2014. (International device/circuits conference. RF inductor device research)

[C10] Y. Wang, Y. Lu, Q. Pan, Z. Hou, L. Wu, W. H. Ki, and C. P. Yue, “A 3-mW 25-Gb/s CMOS transimpedance amplifier with fully integrated low-dropout regulator for 100GbE systems,”in IEEE Radio Frequency Integrated Circuits Symp., pp. 275−278, Jun. 2014.

[C09] Q. Pan, Z. Hou, Y. Wang, Y. Lu, W. H. Ki, K. C. Wang, and C. P. Yue, “A 48-mW 18-Gb/s Fully Integrated CMOS Optical Receiver with Photodetector and Adaptive Equalizer,”in Symp. VLSI Circuits Dig. Tech. Papers, pp. 116−117, Jun. 2014. (Top-level circuits conference. High-speed CMOS optical system with both device and circuits research)

[C08] Y. Wang, Y. Lu, Q. Pan, Z. Hou, L. Wu, W. H. Ki, and C. P. Yue, “A 3-mW 25-Gb/s CMOS transimpedance amplifier with fully integrated low-dropout regulator for 100GbE systems,”in IEEE Radio Frequency Integrated Circuits Symp., pp. 275−278, Jun. 2014.

[C07] Z. Hou, Q. Pan, Y. Wang, L. Wu, and C. P. Yue, “A 23-mW 30-Gb/s digitally programmable limiting amplifier for 100GbE optical receivers,”in IEEE Radio Frequency Integrated Circuits Symp., pp. 279−282, Jun. 2014.

[C06] Q. Pan, Z. Hou, Y. Wang, and C. P. Yue, “A 65-nm CMOS P-well/Deep N-well avalanche photodetector for integrated 850-nm optical receivers,”in IEEE 10th International Conference on ASIC, Oct. 2013. (International device-level conference. Optical photodetector device research)

[C05] L. Sun, Q. Pan, K. C. Wang, and C. P. Yue, “A 25-28 Gbps clock and data recovery system with embedded equalization in 65-nm CMOS,”in Inter. Conference on Solid-State and Integrated Circuit Tech., Oct. 2012.

[C04] Q. Pan, T. J. Yeh, C. Jou, F. L. Hsueh, H. Luong, and C. P. Yue, “A performance study of layout and Vt options for low noise amplifier design in 65-nm CMOS,”in IEEE Radio Frequency Integrated Circuits Symp., pp. 535−538, Jun. 2012. (Top-level circuits conference. High-speed CMOS LNA circuits with device research for TSMC project – transistor study)

[C03] D. Zhang, Z. Wen, W. Li, Q. Pan, “A Large Gain Variable Range, Wide Band width Analog AGC Circuitry for a CMOS GPS Receiver”, Robot World 2008, Seoul, Korea, Oct. 2008.

[C02] Q. Pan, Z. Wen, and W. Li, “A 1.57-GHz low-power low-phase-noise quadrature LC-VCO,”in WCECS 2008, pp. 192‒195, Oct. 2008.

[C01] Q. Pan, Z. Wen, Y. Zhang, and B. Bi, “Phase Noise and Power Optimization of a 2-GHz Differential CMOS LC VCO,”in IEEE Radio Frequency Integration Technology,pp. 258‒261, Aug. 2007.

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